PEB 4364 T V1.2 Infineon Technologies, PEB 4364 T V1.2 Datasheet - Page 99

• Manufacturer Part Number: PEB 4364 T V1.2
• Description: IC SLIC VOICE ACCESS PDSO-36
• Manufacturer: Infineon Technologies
• Series: DuSLICr

Specifications of PEB 4364 T V1.2

• Function: Dual Channel Subscriber Line Interface Circuit (DuSLIC)
• Interface: IOM-2, PCM
• Number Of Circuits: 2
• Voltage - Supply: 3.3 V ~ 5 V
• Current - Supply: 105mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-PDSO
• Includes: DTMF Generator and Decoder, Line Echo Cancellation (LEC), Teletax (TTX) Generation, Universal Tone Detection (UTD)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB4364TV1.2XT; SP000007728

The integrated test and diagnostic functions of the DuSLIC allow to do measurements
with and without an integrator. A measurement with the integrator is started by setting
the bit LM-EN in register LMCR1 from 0 to 1.
Figure 44
When using the integrator for doing levelmeter measurements, the LM-OK bit in register
INTREG2 is used to indicate if the integration has started or is finished, respectively.
After the bit LM-OK is set to 1 again, the result registers can be read to get the
measurement result.
Figure 44
period (transition of LM-EN from 0 to 1) and in relation to a valid result in the result
registers.
The user control software must take care of the mentioned timing relationship:
1. After starting the integrator by setting bit LM-EN from 0 to 1, the bit LM-OK could still
2. After the integration is finished, the bit LM-OK is set to 1 by SLICOFI-2x.
Preliminary Data Sheet
– With SLICOFI-2x Version 1.5, the firmware must wait at least 1 ms before polling
– With SLICOFI-2x Version 1.5, the LM-OK bit is set to 1 synchronous with the
be set to 1 from a previous measurement, which would indicate the end of the
integration period while the actual integration is still going on.
the bit LM-OK.
availability of the LM result. Therefore no delay is necessary before reading the
levelmeter result registers.
shows the timing of the bit LM-OK in relation to the start of the integration
LM-EN
Read LM
result register
LM-OK
Timing LM-OK Bit
After bit LM-EN is set from 0 to 1, bit LM-OK can still
be 1 from a previous measurement:
- SLICOFI-2 V1.5: 1000 µs delay until bit LM-OK is set to 0.
Integration Period
99
Operational Description
Timing_LM-OK
DS3, 2003-07-11
DuSLIC