PEB 4364 T V1.2 Infineon Technologies, PEB 4364 T V1.2 Datasheet - Page 50
PEB 4364 T V1.2
Manufacturer Part Number
PEB 4364 T V1.2
Description
IC SLIC VOICE ACCESS PDSO-36
Manufacturer
Infineon Technologies
Series
DuSLICr
Datasheet
1.PEB_3264_F_V1.4.pdf
(374 pages)
Specifications of PEB 4364 T V1.2
Function
Dual Channel Subscriber Line Interface Circuit (DuSLIC)
Interface
IOM-2, PCM
Number Of Circuits
2
Voltage - Supply
3.3 V ~ 5 V
Current - Supply
105mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
36-PDSO
Includes
DTMF Generator and Decoder, Line Echo Cancellation (LEC), Teletax (TTX) Generation, Universal Tone Detection (UTD)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Other names
PEB4364TV1.2XT
SP000007728
SP000007728
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2.5.5
SLIC-E/-E2 and SLIC-P support internal balanced ringing up to
while SLIC-S supports balanced ringing up to
The ringing signal is generated digitally within the SLICOFI-2x.
Figure 24
In ringing mode, the DC feeding regulation loop is not active. A programmable DC ring
offset voltage is applied to the line instead. During ring bursts, the ringing DC offset and
the ringing signal are summed digitally within SLICOFI-2x in accordance with the
programmed values. This signal is then converted to an analog signal and is applied to
the SLIC. The SLIC amplifies the signal and supplies the line with ringing voltages up to
85 Vrms. In balanced ringing mode, the SLIC uses an additional supply voltage
SLIC-E/-E2/-S and
SLIC-E/-E2/-S and
The maximum ringing voltage that can be achieved is:
for SLIC-E/-E2/-S:
for SLIC-P:
where:
1) In this case V
Preliminary Data Sheet
the open-circuit rms voltage measured directly at pins RING and TIP at the SLIC output with ringer load.
V
For calculation of the ringing voltage at the ringer load, see the Application Note DuSLIC Voltage and Power
Dissipation Calculation and its accompanying MS Excel Sheet for calculation.
TR0,RMS
is the rms voltage measured directly at pins RING and TIP at the SLIC output without any ringer load.
Internal Balanced Ringing via SLICs
V
V
DROP,R
RING,RMS
DROP,T
Balanced Ringing via SLIC-E/-E2, SLIC-S and SLIC-P
V
DC,RING
= V
V
V
BATR
BATR
TR,RMS
for SLIC-P.
V
V
V
= V
for SLIC-P. The total supply span is now
RING,RMS
RING,RMS
DROP,TR
TR0,RMS
V
V
because of the low impedance of the SLIC output (< 1 ). V
=
Tp
Rp
= (
= (
V
v
v
T
V
–
DROP,T
R
V
HR
BATR
V
50
RING,pp
–
V
+
V
–
BATH
V
RING,RMS
= V
V
DROP,R
DROP,TR
Tp
–
- V
V
DROP,TR
Rp
= 45 Vrms
SLIC-E2
–
SLIC-E
SLIC-S
V
V
V
BATH
HR
DC,RING
–
Functional Description
V
SLIC-P
BGND
DC,RING
V
1)
BATR
)/1.41
V
.
RING,RMS
)/1.41
V
DS3, 2003-07-11
HR
ezm140315
= 85 Vrms,
–
V
DuSLIC
BATH
V
TR,RMS
HR
for
for
is
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