PEB 4364 T V1.2 Infineon Technologies, PEB 4364 T V1.2 Datasheet
PEB 4364 T V1.2
Specifications of PEB 4364 T V1.2
SP000007728
Related parts for PEB 4364 T V1.2
PEB 4364 T V1.2 Summary of contents
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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Preliminary Data Sheet Revision History: Previous Version: DS2 Page Subjects (major changes since last revision) Title Product name corrected to Dual Channel Subscriber Line Interface Concept all PEB 3265 version changed from 1.2 to 1.5 all PEB 4264/-2 and PEB ...
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Page 66 “MIPS Requirements for EDSP Capabilities” on Page 66 NLP examples. Page 68 “Three-party Conferencing in DuSLIC-E/-E2/-P” on Page about Multi-party Conferencing added Page 84 “Hardware and Power On Reset” on Page changed to 1.5 ms. Page 85 Figure ...
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Page 205 Table 35 "CRAM Coefficients" on Page nibbles 6 and 7 Page 207 “POP Command” on Page programming added Page 207 “Sequence for POP Register Programming” on Page 207 (because added NLP coefficients) Page 208 “POP Register Overview” on ...
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Page 353 Figure 90, “Internal (balanced and unbalanced) Ringing with SLIC-P” on Page 353: pin TS2/CS changed to TS2/CS, illustration of connection between pins C3 and IO2A modified, SLIC supply voltages added, arrangement of diodes D1 and D2 modified. Page ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 2.8.6 MIPS Requirements for EDSP Capabilities . . . . . . . . . . . . . . . . . . . . . . 66 2.9 Message Waiting Indication in DuSLIC-E/-E2/- ...
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Table of Contents 4 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 6.1.3 Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 DuSLIC Chip Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 43 Continuous Measurement Sequence (AC Level Metering Figure 44 Timing LM-OK Bit ...
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List of Figures Figure 85 PCM Interface Timing – Single-Clocking Mode . . . . . . . . . . . . . . . . . 344 Figure 86 PCM Interface Timing – Double-Clocking Mode . . . ...
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List of Tables Table 1 Codec Feature Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 43 Range of TBN-DEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Preface This Preliminary Data Sheet describes the family of DuSLIC chip sets. Each chip set comprises a dual channel SLICOFI-2x codec and two single- or one dual-channel SLICs. For more DuSLIC related documents, please see our webpage at http://www.infineon.com/duslic. To ...
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Chapter 9, Terminology List of abbreviations and descriptions of symbols. • Chapter 10, Index Preliminary Data Sheet 17 DuSLIC DS3, 2003-07-11 ...
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Overview DuSLIC is a family of communications chip sets. Each chip set comprises one dual-channel SLICOFI-2x codec and two single-channel SLICs or one dual-channel TSLIC highly flexible codec/SLIC solution for an analog line circuit and is ...
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The DuSLIC family allows any combination of the codec and SLIC chips shown in 1 and Table 2. Table 1 Codec Feature Overview Features Number of Voice Channels DTMF Detection Line Echo Cancellation ( ms) Caller-ID Generation Integrated ...
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Table 2 SLIC Feature Overview (cont’d) Features Technology On-Hook Transmission Current Limitation Target Application 1) Same specifications as SLIC-S, but two voice channels 2) Chip marked as PEB 4264 – packaging unit labeled with PEB 4264-2. 3) Same specifications as ...
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For both the DuSLIC-S and DuSLIC-E there are also long-haul versions, offering increased longitudinal balance (60 dB) : – DuSLIC-E2 (using SLIC-E2) – DuSLIC-S2 (using SLIC-S2) Usage of Codecs and SLICs The DuSLIC-S and DuSLIC-S2 chip sets use the ...
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For further information see SLIC SLIC HV SLIC Functions Voltage feeding Transversal current sensing Longitudinal current sensing Overload protection Battery switching Ring amplification On-hook transmission Polarity reversal Figure 1 DuSLIC Chip Set Preliminary Data Sheet Chapter 2.1. SLICOFI-2x LV SLIC ...
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Dual Channel Subscriber Line Interface Concept DuSLIC 1.1 Features • Fully programmable dual-channel codec • Programmable AC and DC characteristics • Integrated Test and Diagnostic Functions (ITDF) • Programmable integrated ringing : Balanced (85 Vrms) and/or Unbalanced (50 Vrms) • ...
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PCM Transmission • IOM-2 or PCM/µC Interface selectable • G.711 A-law / µ-law companding • Specifications: ITU-T G.712, Q.552, LSSGR, TR57 1.2 Typical Applications DuSLIC offers an optimized solution for various applications. applications can ...
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Logic Symbols ITA ITB Line ITACA current ITACB ILA ILB VCMITA VCMITB DCPA DC DCPB loop DCNA DCNB CDCPA CDCNA CDCPB CDCNB VCM VCMS ACPA ACPB AC ACNA loop ACNB C1A C1B Logic control C2A C2B IO1A IO2A IO3A ...
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Tip/Ring interface Power supply Figure 3 Logic Symbol: SLIC-S/SLIC-S2 (V1.1, V1.2), SLIC-E/SLIC-E2 (V1.1) Tip/Ring interface Power supply Figure 4 Logic Symbol: SLIC-E/SLIC-E2 (V1.2) Preliminary Data Sheet TIP PEB 4264 RING PEB 4264-2 PEB 4265 VDD PEB 4265-2 AGND VHR BGND ...
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Tip/Ring interface Power supply Figure 5 Logic Symbol: SLIC-P Preliminary Data Sheet TIP RING PEB 4266 VDD AGND BGND VBATL VBATH VBATR 27 DuSLIC Overview VCMS CEXT IT Line IL current ACP ACN AC & DC DCP feeding DCN C1 ...
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Tip/Ring interface channel A channel A Power supply channel A Tip/Ring interface channel B channel B Power supply channel B Figure 6 Logic Symbol: TSLIC-S/TSLIC-E Preliminary Data Sheet VCMSA CEXTA TIPA RINGA VDDA AGNDA VHRA BGNDA VBATH VBATLA PEB 4364 ...
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Functional Description 2.1 Functional Overview 2.1.1 Basic Functions of all DuSLIC Chip Sets The functions described in this section are integrated into all DuSLIC chip sets (see Figure 7 for DuSLIC-S/-S2 and All BORSCHT functions are integrated: • Battery ...
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The characteristics for the two voice channels within SLICOFI-2x can be programmed independently of each other. The DuSLIC Coefficients Software (DuSLICOS) is provided to automate calculation of coefficients to match different requirements. DuSLICOS also verifies the calculated coefficients. 2.1.2 Additional ...
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SLIC-S/-S2 Current Sensor & Offhook Detection TIP Gain Channel A RING Battery Control Switch Logic SLIC-S/-S2 Channel B Current Sensor & Offhook Detection TIP Gain RING Battery Control Switch Logic Figure 7 Line Circuit Functions in the DuSLIC-S/-S2 SLIC-E/-E2/-P Current ...
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Block Diagram SLICOFI-2/-2S Figure 9 shows the internal block structure of all available SLICOFI-2x codec versions. The Enhanced Digital Signal Processor (EDSP) providing the add-on functions integrated in the SLICOFI-2 (PEB 3265) device. CDCNA CDCPA CDCNB CDCPB Super- ILA ...
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DC Feeding DC feeding with the DuSLIC is fully programmable as shown in Figure 10 shows the signal paths for DC feeding between the SLIC and the SLICOFI-2x: TIP SLIC Channel A RING DCP DCN ACP ACN TIP SLIC ...
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DC Characteristic Feeding Zones The DuSLIC DC feeding characteristic has three different zones: the constant current zone, the resistive zone, and the constant voltage zone. A voltage reserve V Chapter 2.3.7) can be selected to avoid clipping the high ...
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Constant Current Zone In the off-hook state, the feed current must usually be kept at a constant value independent of load (see information to the SLICOFI-2x via the IT pin (input pin for DC control). The SLICOFI-2x compares the ...
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Resistive Zone The programmable resistive zone wide range of applications. The resistive zone is used for very long lines where the battery is incapable of feeding a constant current into the line. The operating point in this case crosses ...
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Constant Voltage Zone The constant voltage zone (see constant voltage to the line. In this case, depends on the load between the Tip and Ring pin. software. In the constant voltage zone, the external resistors stability and protection define ...
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Programmable Voltage and Current Range: DC Characteristics The DC characteristics and all symbols are shown in I TIP/RING Figure 15 DC Characteristics Table 4 DC Characteristics Symbol Programmable Range R 1.8 k … ...
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SLIC Power Dissipation The major portion of the power dissipation in the SLIC can be estimated by the power dissipation in the output stages. The power dissipation can be calculated from – ) SLIC BAT ...
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Necessary Voltage Reserve To avoid clipping AC speech signals as well as AC metering pulses, a voltage reserve V (see Figure 11) must be provided. RES – (see Page RES BAT LIM V ...
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Extended Battery Feeding If the battery voltage is not sufficient to supply the minimum required current through the line even in the resistive zone, the auxiliary positive battery voltage can be used to expand the voltage swing between Tip ...
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AC Transmission Characteristics SLICOFI-2x uses either an IOM PCM digital interface. In receive direction, SLICOFI-2x converts PCM data from the network and outputs a differential analog signal (ACP and ACN) to the SLIC that amplifies the signal ...
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SLICOFI-2x Channel B ITAC TTX filter Impedance matching ACP ACN Figure 20 Signal Flow in Voice Channel (A) 2.4.1 Transmit Path The current sense signal (ITAC) is converted to a voltage by an external resistor. This voltage is first filtered ...
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Matching The SLIC outputs the voice signal to the line (receive direction) and also senses the voice signal coming from the subscriber. The AC impedance of the SLIC and the load impedance need to be matched to maximize power ...
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Ringing Because of the 170 V technology used for the SLIC, a ringing voltage Vrms sinusoidal 100 Vrms trapezoidal can be generated on-chip without the need for an external ringing generator (This ...
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I over one ringer period. This causes the integration result to represent the TRANS DC component of the ring current. If the DC current exceeds the programmed ring trip threshold, SLICOFI-2x generates an interrupt. Ring trip is reliably detected ...
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DuSLIC Ringing Options Application requirements differ with regard to ringing amplitudes, power requirements, loop length, and loads. The DuSLIC options include three different SLICs to ensure the most appropriate ringing methods (see Table 5 Ringing Options with SLIC-S, SLIC-E/-E2 ...
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For SLIC-S2, only external ringing is provided. SLIC-E/-E2 allows balanced ringing Vrms and can, therefore, be used in systems with higher loop impedance. The low-power SLIC-P is optimized for power-critical applications (such as intelligent ISDN network termination). ...
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E xte lta Figure 23 External Ringing Zero Crossing Synchronization Preliminary Data Sheet T T ...
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Internal Balanced Ringing via SLICs SLIC-E/-E2 and SLIC-P support internal balanced ringing up to while SLIC-S supports balanced ringing up to The ringing signal is generated digitally within the SLICOFI-2x. V DROP,T V DC,RING V DROP,R Figure 24 Balanced ...
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Using the DuSLIC chip set, ringing voltages Vrms sinusoidal can be applied, and trapezoidal ringing can be programmed as well. For a detailed application diagram of internal balanced ringing see 353. 2.5.6 Internal Unbalanced Ringing with SLIC-P ...
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In both balanced and unbalanced ringing modes, SLICOFI-2 automatically applies and removes the ringing signal during zero-crossing. This reduces noise and cross-talk to adjacent lines. 2.5.7 External Unbalanced Ringing SLICOFI-2x supports external (balanced or unbalanced) ringing for higher ringing voltage ...
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In Sleep/Power Down mode (PDRx), a similar mechanism is used. In this mode, the internal current sensor of the SLIC is switched off to minimize power consumption. The loop current is therefore fed and sensed through 5 k resistors ...
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Metering One of two different metering methods may be specified: • Metering by sinusoidal bursts of either 12 kHz or 16 kHz • Polarity reversal of Tip and Ring. 2.7.1 Metering by 12/16 kHz Sinusoidal Bursts To satisfy worldwide ...
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Metering by Polarity Reversal SLICOFI-2/-2S also supports metering by polarity reversal by changing the actual polarity of the voltages on the TIP/RING lines. Polarity reversal is activated by switching the REVPOL bit in register BCR1 to one or by ...
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DuSLIC Enhanced Signal Processing Capabilities The signal processing capabilities described in this section are implemented by an Enhanced Digital Signal Processor (EDSP), with the exception of DTMF generation. Each function can be individually enabled or disabled for each DuSLIC ...
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The enhanced Signal Processing capabilities are available only for the DuSLIC-E/-E2/-P versions, with an exception of DTMF generation. The DTMF generation is available for all DuSLIC versions. The functions of the EDSP are configured and controlled by POP register settings ...
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Table 6 shows the performance characteristics of the DTMF decoder algorithm: Table 6 Performance Characteristics of the DTMF Decoder Algorithm No. Characteristic 1 Valid input signal detection level 2 Input signal rejection level 3 Positive twist accept 4 Negative twist ...
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In the event of pauses < 20 ms: • If the pause is followed by a tone pair with the same frequencies as before, this is interpreted as drop-out. • If the pause is followed by a tone pair with ...
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DuSLIC-E/-E2/-P FSK Generation Different countries use different standards to send Caller ID information. The DuSLIC-E/-E2/-P chip set is compatible with the widely used Bellcore GR-30- CORE, British Telecom (BT) SIN227, SIN242, and the UK Cable Communications Association (CCA) specification TW/P&E/312 ...
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Bellcore On-hook Caller ID Physical Layer Transmission First Ring Burst Channel Seizure A B Parameter Header Message Message Parameter Type Length 1 Type Message Header 1 Message length equals the number of bytes to follow in the message body, excluding ...
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If this bit is set, write at least BRS + 2 bytes (see POP register CIS-BRS) of Caller ID data but not more than 48 bytes to the Caller ID sender buffer register CIS-DAT. 6. Wait for the next ...
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Line Echo Cancellation in DuSLIC-E/-E2/-P The DuSLIC-E/-E2/-P contains an adaptive Line Echo Cancellation (LEC) unit for the cancellation of near end echoes. With the adaptive balancing of the LEC unit, the Transhybrid Loss can be improved ...
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If the adaptation of the shadow filter is performed better than the adaptation of the actual filter by a value of more than DeltaQ, then the shadow filter coefficients will be copied to the actual filter. ...
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NLP bypasses local DTMF signals, but it would be a good strategy to only enable the NLP after the call has been completely established (far end talker connected). 2.8.5 Universal Tone Detection in DuSLIC-E/-E2/-P Each channel of the DuSLIC-E/-E2/-P has ...
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The UTDR-OK or UTDX-OK bit (register INTREG3 on following conditions hold for a time span of at least RTime RBRKTime: 1. The in-band signal exceeds a programmable level Lev 2. The difference of the in-band and the out-of-band signal levels ...
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Example: • All algorithms for all channels enabled and LEC Length = 8 ms (LEN = 64): 33.32 MIPS total computing load exceeding the 32 MIPS limit! • All algorithms for all channels enabled and LEC Length = 4 ms ...
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The glow lamp circuit also requires a resistor (R phone. When activated, the lamp must be able to either blink or remain on constantly. In non-DuSLIC-E/-E2/-P solutions, the telephone ringer may respond briefly if the signal slope is too steep; ...
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This facility is available in PCM/ C mode only. The PCM control registers PCMR1 through PCMR4 and PCMX1 through PCMX4 control the time slot assignment and PCM highway selection, while the bits PCMX-EN, CONF-EN, and CONFX-EN in the BCR3 register ...
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Table 9 Conferencing Modes: Receive Channels (cont’d) Configuration Registers Mode PCMX- EN External 0 Conference External 1 Conference + PCM Active Internal 0 Conference Table 10 Conferencing Modes: Transmit Channels Configuration Registers Mode PCMX- EN PCM Off 0 PCM Active ...
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PCM Off After a reset power down mode, there is no communication via the PCM highways. Also, when selecting new time slots recommended to switch off the PCM line drivers by setting the control bits to ...
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Table 11 Possible Modes in PCM/µC Interface Mode: Receive Channels Mode Configuration Bits PCM16K LIN PCM 0 0 LIN 0 1 PCM16 1 0 LIN16 Time slot Empty cells in the table indicate ...
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PCM16 Mode Mode for higher data transmission rate of PCM encoded data using a 16 kHz sample rate (only in PCM/ C Interface mode with the PCMX-EN bit in the BCR3 register set to one). In this mode, the channels ...
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Operational Description 3.1 Overview of all DuSLIC Operating Modes Table 13 Overview of all DuSLIC Operating Modes SLICOFI-2x Mode SLIC-S/ SLIC-S2 Sleep (SL) – Power Down PDRH Resistive (PDR) Power Down PDH High Impedance (PDH) Active High ACTH (ACTH) ...
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Table 13 Overview of all DuSLIC Operating Modes (cont’d) SLICOFI-2x Mode SLIC-S/ SLIC- Active with ACTx Metering Ground Start HIT 3) Ring Pause ACTR 1) CIDD = Data Downstream Command/Indication Channel Byte (IOM-2 Interface) CIOP = Command/Indication Operation ...
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SLICOFI-2 wakes up. In IOM-2 mode, the identification request can be used as a wake up signal as this command is independent of the internal clock. In the PCM/ C mode ...
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Ringing If the SLICOFI-2x is switched to Ringing mode, the SLIC is switched to ACTR mode. With the SLIC-P connected to the SLICOFI-2, the Ring on Ring (ROR) mode allows unbalanced internal ringing on the Ring wire. The Tip wire ...
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Operating Modes for the DuSLIC-S/-S2/-SE/-SE2 Chip Set Table 14 DuSLIC-S/-S2/-SE/-SE2 Operating SLICOFI-2S SLIC-S/S2 /SLICOFI-2S2 /SLIC-E/E2 Mode Mode PDH PDH Power Down PDRH Resistive 1) – PDRHL Active Low ACTL (ACTL) Active High ACTH (ACTH) Active Ring ACTR (ACTR) Preliminary ...
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Table 14 DuSLIC-S/-S2/-SE/-SE2 Operating SLICOFI-2S SLIC-S/S2 /SLICOFI-2S2 /SLIC-E/E2 Mode Mode Ringing (Ring) ACTR Ring Pause ACTR HIRT HIRT Active with HIR HIR Active with HIT HIT 1) Load external C for switching from PDRH to ACTH in on-hook mode. V ...
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Operating Modes for the DuSLIC-E/-E2/-ES/-ES2 Chip Set Table 15 DuSLIC-E/-E2/-ES/-ES2 Operating SLICOFI-2 SLIC-E/E2 Mode /SLIC-S/S2 Mode PDH PDH Sleep PDRH Power PDRH Down Resistive 1) – PDRHL Active Low ACTL (ACTL) Active ACTH High (ACTH) Active ACTR Ring (ACTR) ...
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Table 15 DuSLIC-E/-E2/-ES/-ES2 Operating SLICOFI-2 SLIC-E/E2 Mode /SLIC-S/S2 Mode Ringing ACTR (Ring) Ring ACTR Pause HIRT HIRT Active with HIR HIR Active with HIT HIT 1) Load external C for switching from PDRH to ACTH in on-hook mode V … ...
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Operating Modes for the DuSLIC-P Chip Set Table 16 DuSLIC-P Operating SLICOFI-2 SLIC-P SLIC-P Mode Mode Internal Supply Voltages PDH PDH BATR V Sleep PDRH BATH V Sleep PDRR BATR V Power PDRH BATH Down Resistive ...
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Table 16 DuSLIC-P Operating SLICOFI-2 SLIC-P SLIC-P Mode Mode Internal Supply Voltages Active Ring ACTR BATR (ACTR) V Ringing ACTR BATR (Ring) V Ringing ROR BATR (Ring) V Ringing ROT BATR (Ring) V Ring Pause ACTR, BATR ...
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Reset Mode and Reset Behavior 3.5.1 Hardware and Power On Reset A reset of the DuSLIC is initiated by a power-on reset hardware reset. Hardware reset requires setting the signal at RESET input pin to low ...
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Reset signal at pin RESET µs) rej Chip reset: - all I/O pins deactivated - all outputs inactive (e.g. DXA/DXB) - internal PLL stopped - internal clocks deactivated Figure 36 DuSLIC Reset Sequence Preliminary Data Sheet ...
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Software Reset When performing a software reset, the DuSLIC runs the reset routine and sets the default settings of the configuration registers. The software reset can be performed individually for each channel. Table 17 Default DC and AC Values ...
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Table 17 Default DC and AC Values (cont’d) SRend2 1/512 – DUP 10 ms DUP-IO 16.5 ms SR-Time IM-Filter 900 TH-Filter TH – GER L 0 dBr X L –7 dBr R ATTX 2.5 Vrms f 16 ...
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Interrupt Handling Attention: Even if interrupts are not used in the system application, the user has to clear the reset interrupt after each power-up reset. SLICOFI-2x provides extensive interrupt data for the host system. Interrupt handling is performed by ...
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rru iste ith rru p t ...
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Power Management and Operating Modes In many applications the power dissipated on the linecard is a critical parameter. In large systems it is the mean power value (taking into account traffic statistics and line length distribution) that determines cooling ...
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SLICOFI-2x Power Dissipation For optimized power consumption, unused EDSP functions must be switched off. Typical power dissipation values for different operating modes of the SLICOFI-2x can be found in the device data sheets. 3.7.2 SLIC Power Dissipation The SLIC’s ...
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Active Modes In all active modes, the total power dissipation usually is dominated by the line current P part (eq. 2); the quiescent power typically is below 150 mW. O For any line with total resistance ...
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Ringing Mode Basically the considerations above are also valid in Ringing Mode. The only difference results from the fact, that in Ringing a large sinusoidal signal is applied to a complex RC load (compared with DC drive of an ...
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Integrated Test and Diagnostic Functions (ITDF) 3.8.1 Introduction Subscriber loops are affected by a variety of failures that must be monitored. Monitoring the loop requires access to the subscriber loop and requires test equipment in place that is capable ...
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Diagnostics DuSLIC incorporates signal generators and test features implemented to accomplish a variety of diagnostic functions. The SLICOFI-2x device generates all test signals, processes the information that comes back from the SLIC, and provides the data to a higher ...
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Ring generator ( 300 Hz) Refer to the CRAM coefficient Figure 40 shows the entire level metering block for AC and DC SIGMA PREFI DELTA ITAC 4 MHz PCM IN: Receive Data from ...
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Result Register Data Format The result of any measurement can be read via the result registers LMRES1/2. This gives a 16-bit value, with LMRES1 being the high and LMRES2 being the low byte. The result is coded in 16-bit ...
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Continuous Measurement Sequence (DC Level Metering Figure 42 Continuous Measurement ...
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The integrated test and diagnostic functions of the DuSLIC allow to do measurements with and without an integrator. A measurement with the integrator is started by setting the bit LM-EN in register LMCR1 from LM-EN LM-OK Read ...
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DC Level Metering The path of the DC level meter is shown in will be determined and prepared depending on certain configuration settings. The selected input signal becomes digitized after pre-filtering and analog-to-digital conversion. The DC level meter is ...
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The shift factor K is set in the CRAM (offset address 0x76): INTDC CRAM: Address 0x76: LMDC2/LMDC1 Address 0x77: 0/LMDC3 LMDC1, LMDC2 and LMDC3 are 4-bit nibbles which contain K Table 20 K Setting Table INTDC LMDC1 LMDC2 8 8 ...
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CRAM: Address 0x73: RGF2/RGF1 Address 0x74: RGA1/RGF3 RGF1, RGF2 and RGF3 are 4-bit nibbles which control the ring frequency f RGA1 is a 4-bit nibble that is calculated by DuSLICOS and which controls the ringer amplitude (see DuSLICOS byte file). ...
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LM = 0.2863 Result • Example for negative value of LM LM-VAL-H = “1001 1001" = 0x99 LM-VAL-L = “0110 0010" = 0x62 LM = 0x9962 = –26270 Value LM = –0.8017 Result Table 22 Level Meter Results with and ...
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DC current on pin IL (bits LM-SEL[3:0] = 1001) 3) Voltage on IO3 referenced Voltage on IO4 referenced Voltage on IO4 – IO3 referenced output voltage at SLIC measured ...
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The offset registers OFR1 and OFR2 must be programmed to the value LM Value OFFSET = – ------------------------------------------------------------ - N Samples where OFR1 is the high byte and OFR2 is the low byte of the 16 bit word OFFSET. ...
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K can be set via coefficient LM-AC: INTAC CRAM: Address 0x34: CG1/LM-AC LM- 4-bit nibble which contains K CG1 is a 4-bit nibble that is calculated by DuSLICOS and which controls the conference gain (see DuSLICOS byte file). ...
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Register BCR4: AR-DIS = 1, AX-DIS = 1, TH-DIS = 1, IM-DIS = 1, FRR-DIS = 1, FRX-DIS = 1 Register TSTR4: OPIM- OPIM- Register LMCR1: TEST- This setting results in a receive gain ...
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K Constant factor from Digital to Analog DA K Amplification factor of the SLIC AC,SLIC V Voltage at D/A converter referred to digital full scale DAC Trapez Crest factor of the trapezoidal signal Output voltage between Tip and Ring: V ...
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The level meter threshold can be calculated with DuSLICOS or may be taken from Table 26. CRAM: Address 0x2C: LMTH2/LMTH1 Address 0x2D: 0/LMTH3 (LMTH1, LMTH2 and LMTH3 are 4 bit nibbles) Table 26 Threshold Setting Table LMTH1 LMTH2 1 0 ...
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Current Offset Error Compensation The current offset error caused by the current sensor inside the SLIC can be compensated by programming the compensation registers OFR1 and OFR2 accordingly. The current offset error can be measured with the DC level ...
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Loop Resistance Measurements The DC loop resistance can be determined by supplying a constant DC voltage V to the Ring- and Tip line and measuring the DC loop current via IT pin. The following steps are necessary to accomplish ...
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Assumption: • Loop resistance R = 1000 ; R loop • Ring offset RO2 = 60 V (CRAM coefficient set accordingly). Ring offset RO2 is selected by setting bits RNG-OFFSET[1:0] in register LMCR3 to 10. The exact value for the ...
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Differential Resistance Calculation prog I = ------------------------------------------------ measure normal – prog I = --------------------------------------------------- - measure reverse – I measure normal measure reverse prog R = ------------------------------------------------------------------------------------------- - I I – measure normal ...
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This can be achieved by programming the ring generator delay appropriately (see DuSLICOS DC Control Parameter 2/4). The integration time for the current measurement is determined by the ring frequency (refer to CRAM coefficients, see Table ...
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Example • Assumptions: – Capacitance as object to be determined: C – Resistor R in series to C Measure – Measure Measure • Calculating parameter values: – Choose Ring Offset voltage 1: RO1 = 70 V (Start ...
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Enable the ramp generator by setting bit RAMP-EN in register LMCR2 to 1. • Apply Ring Offset voltage RO2 to Ring and Tip line by setting bits RNG-OFFSET[1:0] in register LMCR3 to 10. • Enable the level meter by ...
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To select the input information that taken for the measurement, set bits LM-SEL[3:0] in configuration register LMCR2 (see Table 27 Measurement Input Selection LM-SEL[3:0] in Register LMCR2 1010 1011 1111 The measurement is accomplished ...
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Maximum level of the expected foreign voltages • Voltage range of IO3 and IO4 = V The voltage on IO3 or IO4 is measured with a reference to VCM. Hence, an input voltage either input pin ...
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Signal Path and Test Loops The following figures show the main AC and DC signal path and the integrated analog and digital loops of the DuSLIC-E/-E2/-P and DuSLIC-S/-S2. Please note the interconnections between the AC and DC pictures of ...
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AC-DLB-32K COX16 a AX2 HPX2 HPX-DIS AX-DIS AR-DIS b AR2 COR-64 ITAC TTX Adapt. Programmable via CRAM TTX-12K TTX-DIS PD-TTX-A Not Programmable SWITCH Always available ACN/ACP Available only when bit SWITCH TEST- Figure 50 AC Test Loops DuSLIC-S/-S2/-SE/-SE2 ...
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DC Test Loops LM-SEL[3: IO3 PD-DC-PR IO4 PREFI IO4 – IO3 VDD Offset PD-DCBUF PC-POFI-HI DCN/DCP DC BUF Programmable via CRAM Not Programmable Always available SWITCH Available only when bit SWITCH TEST- Figure 51 DC ...
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Interfaces The DuSLIC offers two different interfaces to connect to a digital network: • PCM Interface combined with a serial microcontroller interface • IOM-2 Interface. The PCM/IOM-2 pin selects the interface mode. – PCM/IOM IOM-2 mode. – ...
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FSC PCLK DRA Time Slot DXA TCA Detail A DETAIL A: FSC PCLK DRA DXA TCA Figure 52 General PCM Interface Timing The data rate of the interface can vary from 2*128 kbit/s to 2*8192 kbit/s ...
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... Valid PCLK clock rates are Ordering No. B115-H6377-X-X-7600, published by Infineon Technologies. Preliminary Data Sheet ICs for Communications Time Slots [per highway 128 f/64 f/128 64 kHz (2 n 128) 124 DuSLIC Interfaces 1) User’s Manual ...
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FSC PCLK Bit 7 Time-Slot 0 PCLK Figure 53 Setting the Slopes in Register PCMC1 Preliminary Data Sheet transmit slope receive slope Single Clock Mode DBL NO- PCMC1: CLK SLOPE SLOPE DRIVE DBL- X- ...
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Control of the Active PCM Channels The SLICOFI-2x offers additional functionality on the PCM Interface including three-party conferencing and a 16 kHz sample rate. Five configuration bits and the PCM configuration registers control the activation of the PCM transmit ...
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Serial Microcontroller Interface The microcontroller interface consists of four lines: CS, DCLK, DIN and DOUT. CS: A synchronization signal starting a read or write access to SLICOFI-2x. DCLK: A clock signal (up to 8.192 MHz) supplied to SLICOFI-2x. DIN: ...
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CS n Data Bytes write command DIN Comm 1st DCLK CS Single Byte write command Comm 1st DIN Figure 54 Serial Microcontroller Interface Write Access Note: Serial Microcontroller Interfaces Write Access shown in bytes and single byte commands. CS DIN ...
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... FSC: A Frame Synchronization Signal (8 kHz) supplied to SLICOFI-2x. DCL: A Data Clock Signal (2048 kHz or 4096 kHz) supplied to SLICOFI-2x. SLICOFI-2x handles data as described in the IOM-2 specification for analog devices. This specification is available on request from Infineon Technologies. Preliminary Data Sheet 129 DuSLIC Interfaces DS3, 2003-07-11 ...
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FSC DCL DD TS0 DU TS0 Detail A DD Voice Channel A DU Voice Channel A Figure 56 IOM-2 I/F Timing for Voice Channels (Per 8 kHz Frame) The information is multiplexed into frames that are transmitted ...
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FSC DCL 4096 kHz DD TS0 TS0 DU Detail B Detail B FSC DCL DD/DU Bit N Figure 57 IOM-2 Interface Timing (DCL = 4096 kHz, Per 8 kHz Frame) FSC DCL 2048 kHz TS0 DD DU TS0 Detail C ...
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Table 30 IOM-2 Time Slot Assignment TS2 TS1 MHz or 4 MHz DCL is selected by the SEL24 pin: SEL24 = 0: DCL ...
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IOM-2 Interface Monitor Transfer Protocol Monitor Channel Operation The monitor channel is used for the transfer of maintenance information between two functional blocks. Using two monitor control bits (MR and MX) per direction, the data is transferred in a ...
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Monitor Handshake Procedure The monitor channel works in three states Idle state: A pair of inactive (set and MX bits during two or more consecutive frames: End of Message (EOM) Sending state: MX bit is activated (set ...
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MR + MXR Idle MR ° MXR ° RQT st 1 byte MR ° RQT ° RQT th n byte MR ack ° RQT MR wait for MR ...
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Idle ° byte MX rec byte MX ° LL valid new byte Figure 61 State Diagram of the SLICOFI-2x Monitor Receiver ...
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Address Byte Messages to and from the SLICOFI-2x start with the following byte: Bit 4.2.2 SLICOFI-2x Identification Command For the IOM-2 Interface only, a two-byte identification command is defined for analog line IOM-2 devices to unambiguously ...
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Serial µController Interface IOM-2 Interface 1.536 MHz DCLK FSC 8 kHz DCLK/1.536 MHz DD/768 kBit/s DU/768 kBit/s FSC SLICOFI-2x TS0 TS1 TS2 high imp. high imp. high imp. DXA or DXB IOM-2 DU IOM Channel 0 ...
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It has also to be considered that the SLICOFI-2x offers 3.3 V logic levels for the PCM voice data. If the driving capability or the 3.3 V level of the SLICOFI-2x are not sufficient, an external driver/levelshifter has to be ...
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SLICOFI-2x Command Structure and Programming With the commands described in this chapter, the SLICOFI-2x can be programmed, configured, and tested very flexibly via the microcontroller interface or via the IOM-2 interface monitor channel. The command structure uses one-byte and ...
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M2, M1, M0: General Operating Mode Table 31 Command/Indication Operation (CIOP ADR[2:0] Channel address for the ...
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CMD[2: CMD[2: Structure of the Second Command Byte The second command byte specifies a particular SOP, COP, or POP command, depending on the CMD[2:0] bits of the first command byte. In the ...
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Overview of Commands SOP STATUS OPERATION Bit 7 6 Byte Byte 2 COP COEFFICIENT OPERATION Bit 7 6 Byte Byte 2 POP POP OPERATION (only SLICOFI-2 PEB 3265 used for DuSLIC-E/-E2/-P) Bit 7 ...
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SLICOFI-2 Command Structure and Programming This section describes only the SLICOFI-2 PEB 3265 command structure and programming. 5.2.1 SOP Command The Status Operation (SOP) command provides access to the configuration and status registers of the SLICOFI-2. Common registers change ...
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XCR H EDSP-EN ASYNCH-R 07 INTREG1 H INT-CH HOOK 08 INTREG2 H LM-THRES READY 09 INTREG3 H DTMF-OK 0A INTREG4 H EDSP-FAIL 0 0B CHKR1 H SUM-OK 0C CHKR2 H 0D LMRES1 H 0E LMRES2 H 0F FUSE2 H ...
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MASK H READY-M HOOK-M 12 IOCTL1 H IO[4:1]-INEN 13 IOCTL2 H IO[4:1]-OEN 14 IOCTL3 H DUP[3:0] 15 BCR1 H HIR HIT 16 BCR2 H REXT-EN SOFT-DIS 17 BCR3 H MU-LAW LIN 18 BCR4 H TH-DIS IM-DIS 19 BCR5 H ...
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LMCR1 H TEST-EN LM-EN 1D LMCR2 H LM-NOTCH LM-FILT 1E LMCR3 H AC-SHORT- RTR-SEL EN 1F OFR1 H 20 OFR2 H 21 PCMR1 H R1-HW 22 PCMR2 H R2-HW 23 PCMR3 H R3-HW 24 PCMR4 H R4-HW 25 PCMX1 ...
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PCMX2 H X2-HW 27 PCMX3 H X3-HW 28 PCMX4 H X4-HW 29 TSTR1 H PD-AC-PR PD-AC-PO 2A TSTR2 H PD-DC- TSTR3 TSTR4 H OPIM-AN OPIM-4M 2D TSTR5 Preliminary Data Sheet ...
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SOP Register Description 00 REVISION Revision Number (read-only) H Bit 7 6 REV[7:0] Current revision number of the SLICOFI-2. 01 CHIPID 1 Chip Identification 1 (read-only) H Bit CHIPID 2 Chip Identification 2 (read-only) H Bit ...
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PCMC1 PCM Configuration Register 1 H Bit 7 6 DBL-CLK X-SLOPE R-SLOPE NO-DRIVE-0 DBL-CLK Clock mode for the PCM interface (see DBL-CLK = 0 DBL-CLK = 1 X-SLOPE Transmit slope (see X-SLOPE = 0 X-SLOPE = 1 R-SLOPE Receive ...
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XCR Extended Configuration Register H Bit 7 6 EDSP- ASYNC EN H-R EDSP-EN Enables the Enhanced Digital Signal Processor EDSP. EDSP- EDSP- ASYNCH-R Enables asynchronous ringing in case of internal or external ringing. ASYNCH-R = ...
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INTREG1 Interrupt Register 1 (read-only) H Bit 7 6 INT-CH HOOK INT-CH Interrupt channel bit. This bit indicates that the corresponding channel caused the last interrupt. Will be automatically set to zero after all interrupt registers were read. INT-CH ...
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ICON Constant current information. Filtered by DUP-IO counter and interrupt generation masked by the ICON-M bit. A change of this bit generates an interrupt. ICON = 0 ICON = 1 VTRLIM Exceeding of a programmed voltage threshold for the TIP/RING ...
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INTREG2 Interrupt Register 2 (read-only) H Bit 7 6 LM- READY RSTAT THRES After a hardware reset, the RSTAT bit is set and generates an interrupt. Therefore the default value of INTREG2 is 20 value changes ...
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INTREG3 Interrupt Register 3 (read-only) H Bit 7 6 DTMF- OK DTMF-OK Indication of a valid DTMF Key by the DTMF receiver. A change of this bit generates an interrupt. DTMF- DTMF- DTMF-KEY[4:0] Valid DTMF ...
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Table 32 Valid DTMF Keys (Bit DTMF-KEY4 = 1) (cont’ [Hz] [Hz] DIGIT LOW HIGH 852 1633 C 941 1633 D UTDR-OK Universal Tone Detection Receive (such as Fax/Modem tones) UTDR- UTDR- UTDX-OK Universal ...
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INTREG4 Interrupt Register 4 (read-only) H Bit 7 6 EDSP- 0 FAIL EDSP-FAIL Indication of a malfunction of the Enhanced Digital Signal Processor EDSP. EDSP-FAIL = 0 Enhanced Digital Signal Processor EDSP normal EDSP-FAIL = 1 Enhanced Digital Signal ...
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CIS-REQ Caller ID data request. An interrupt is only generated if the CIS-REQ bit changes from CIS-REQ = 0 CIS-REQ = 1 CIS-ACT Caller ID generator active. This is a status bit only. No interrupt will be ...
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CHKR1 Checksum Register 1 (High Byte) H (read-only) Bit 7 6 SUM- OK SUM-OK Information about the validity of the checksum. The checksum is valid if the internal checksum calculation is finished. Checksum calculation: SUM- SUM-OK = ...
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LMRES1 Level Metering Result 1 (High Byte) H (read-only) Bit 7 6 LM-VAL-H[7:0] LM result High Byte (selected by the LM-SEL bits in the LMCR2 register) 0E LMRES2 Level Metering Result 2 (Low Byte) H (read-only) Bit 7 6 ...
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MASK Mask Register H Bit 7 6 READY HOOK -M -M The mask bits in the mask register only influence the generation of an interrupt. Even if the mask bit is set to 1, the corresponding status bit in ...
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OTEMP-M Mask bit for Thermal Overload Warning OTEMP bit OTEMP OTEMP SYNC-M Mask bit for Synchronization Failure SYNC-FAIL bit SYNC SYNC Preliminary Data Sheet A change of the OTEMP bit from 0 ...
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IOCTL1 I/O Control Register 1 H Bit 7 6 IO[4:1]-INEN The mask bits IO[4:1]-M only influence the generation of an interrupt. Even if the mask bit is set to 1, the corresponding status bit in the INTREGx registers is ...
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IO2-M Mask bit for IO2-DU bit IO2 IO2 IO1-M Mask bit for IO1-DU bit IO1 IO1 Preliminary Data Sheet Each change of the IO2 bit generates an interrupt. Changes of the IO2 ...
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IOCTL2 I/O Control Register 2 H Bit 7 6 IO[4:1]-OEN IO4-OEN Enabling output driver of the IO4 pin IO4-OEN = 0 IO4-OEN = 1 IO3-OEN Enabling output driver of the IO3 pin IO3-OEN = 0 IO3-OEN = 1 IO2-OEN ...
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IO2-DD Value for the programmable I/O pin IO2 if programmed as an output pin. IO2- IO2- IO1-DD Value for the programmable I/O pin IO1 if programmed as an output pin. IO1- IO1- ...
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BCR1 Basic Configuration Register 1 H Bit 7 6 HIR HIT HIR This bit modifies different basic modes. In ringing mode, an unbalanced ringing on the RING wire (ROR) is enabled. In Active mode, high impedance on the RING ...
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ACTR Selection of extended battery feeding in Active mode. Also changes the voltage in Power Down Resistive mode for SLIC-P. In this case, V SLIC-P and V HR ACTR = 0 ACTR = 1 ACTL Selection of the low battery ...
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For SLIC-P two selections are possible. • The standard SLIC-P selection automatically uses the IO2 pin of the SLICOFI-2 to control the C3 pin of the SLIC-P. By using pin C3 as well as the pins C1 and C2, all ...
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BCR2 Basic Configuration Register 2 H Bit 7 6 REXT- SOFT- EN DIS REXT-EN Enables the use of an external ring signal generator. Synchronization is done via the RSYNC pin and the Ring Burst Enable signal is transferred via ...
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AC-XGAIN Analog gain in transmit direction (should be set to zero). AC-XGAIN = 0 AC-XGAIN = 1 UTDX-SRC Universal Tone Detector transmit source. Any change of bit UTDX-SRC only becomes effective, if bit UTDX-EN in register BCR5 is changed from ...
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PDOT-DIS Power Down Overtemperature Disable PDOT-DIS = 0 PDOT-DIS = 1 Preliminary Data Sheet When overtemperature is detected, the SLIC is automatically switched into Power Down High Impedance mode (PDH). This is the safe operation mode for the SLIC-E/-E2/-P in ...
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BCR3 Basic Configuration Register 3 H Bit 7 6 MU- LIN LAW MU-LAW Selects the PCM Law MU-LAW = 0 MU-LAW = 1 LIN Voice transmission in a 16-bit linear representation for test purposes. Note: Voice transmission on the ...
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CONF-EN Selection of three-party conferencing for this channel. The voice data of this channel and the voice data from the corresponding conferencing channels (see Chapter 2.10). CONF- CONF- LPRX-CR Select CRAM coefficients for the filter characteristic ...
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BCR4 Basic Configuration Register 4 H Bit 7 6 TH-DIS IM-DIS TH-DIS Disables the TH filter. TH-DIS = 0 TH-DIS = 1 IM-DIS Disables the IM filter. IM-DIS = 0 IM-DIS = 1 AX-DIS Disables the AX filter. AX-DIS ...
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HPR-DIS Disables the high-pass filter in receive direction. HPR-DIS = 0 HPR-DIS = 1 Preliminary Data Sheet High-pass filter is enabled. High-pass filter is disabled (H 176 DuSLIC = 1). HPR DS3, 2003-07-11 ...
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BCR5 Basic Configuration Register 5 H Bit 7 6 UTDR- UTDX UTDR-EN Enables the Universal Tone detection in receive direction. UTDR- Universal Tone detection is disabled. UTDR- Universal Tone detection is enabled. UTDX-EN ...
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LEC-OUT Line Echo Cancellation result for transmit path. LEC-OUT = 0 Line Echo Cancellation result used for DTMF only. LEC-OUT = 1 Line Echo Cancellation result fed to transmit path. LEC-EN Line Echo Cancellation LEC- LEC- ...
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DSCR DTMF Sender Configuration Register H Bit 7 6 DG-KEY[3:0] DG-KEY[3:0] Selects one of sixteen DTMF keys generated by the two tone generators. The key will be generated if TG1-EN and TG2-EN are 1. Table 33 DTMF Keys f ...
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PTG Programmable coefficients for tone generators will be used. PTG = 0 PTG = 1 TG2-EN Enables tone generator two TG2- TG2- TG1-EN Enables tone generator one TG1- TG1- Reserved H ...
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LMCR1 Level Metering Configuration Register 1 H Bit 7 6 TEST- LM-EN EN TEST-EN Activates the SLICOFI-2 test features controlled by test registers TSTR1 to TSTR5. TEST- TEST- Note: The Test Register bits can be ...
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LM-ONCE Level metering execution mode. LM-ONCE = 0 LM-ONCE = 1 LM-MASK Interrupt masking for level metering. LM-MASK = 0 LM-MASK = 1 DC-AD16 Additional digital amplification in the DC AD path for level metering. DC-AD16 = 0 DC-AD16 = ...
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LMCR2 Level Metering Configuration Register 2 H Bit 7 6 LM- LM- NOTCH FILT LM-NOTCH Selection of a notch filter instead of the band-pass filter for level metering. LM-NOTCH = 0 LM-NOTCH = 1 LM-FILT Enabling of a programmable ...
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LM-SEL[3: level metering in receive and transmit LM-SEL[3: Not used LM-SEL[3: current on IL LM-SEL[3: Voltage on IO3 ...
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LMCR3 Level Metering Configuration Register 3 H Bit 7 6 AC- RTR- SHORT SEL -EN AC-SHORT-EN The input pin ITAC will be set to a lower input impedance so that the capacitor makes it more silent during conversation. AC-SHORT-EN ...
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RNG- Ring Offset Voltage in Given Mode OFFSET[1:0] Active ACTH ACTL 0 0 Voltage given by DC regulation 0 1 Ring Offset RO1/2 (no DC regulation Ring Offset RO2/2 (no DC regulation Ring Offset RO3/2 (no ...
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RNG-OFFSET[1:0] RAMP-EN (register LMCR2) LM-EN (register LMCR1) Generated Ring Offset (RO) Voltage RO3 = 120 V RO2 = 40 V RO1 = 20 V Figure 63 Example for Switching Between Different Ring Offset Voltages The three programmable Ring Offsets are ...
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OFR1 Offset Register 1 (High Byte) H Bit 7 6 OFFSET-H[7:0] Offset register High Byte. 20 OFR2 Offset Register 2 (Low Byte) H Bit 7 6 OFFSET-L[7:0] Offset register Low Byte. The value of this register together with OFFSET-H ...
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PCMR1 PCM Receive Register 1 H Bit 7 6 R1- HW This register is not applicable and is not used in IOM-2 mode only enabled in PCM/microcontroller mode. R1-HW Selection of the PCM highway for receiving PCM ...
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PCMR2 PCM Receive Register 2 H Bit 7 6 R2- HW This register is not applicable and is not used in IOM-2 mode only enabled in PCM/microcontroller mode. R2-HW Selection of the PCM highway for receiving conferencing ...
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PCMR3 PCM Receive Register 3 H Bit 7 6 R3- HW This register is not applicable and is not used in IOM-2 mode only enabled in PCM/microcontroller mode. R3-HW Selection of the PCM highway for receiving conferencing ...
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PCMR4 PCM Receive Register 4 H Bit 7 6 R4- HW This register is not applicable and is not used in IOM-2 mode only enabled in PCM/microcontroller mode. R4-HW Selection of the PCM highway for receiving conferencing ...
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PCMX1 PCM Transmit Register 1 H Bit 7 6 X1- HW This register is not applicable and is not used in IOM-2 mode only enabled in PCM/microcontroller mode. X1-HW Selection of the PCM highway for transmitting PCM ...
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PCMX2 PCM Transmit Register 2 H Bit 7 6 X2- HW This register is not applicable and is not used in IOM-2 mode only enabled in PCM/microcontroller mode. X2-HW Selection of the PCM highway for transmitting conferencing ...
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PCMX3 PCM Transmit Register 3 H Bit 7 6 X3- HW This register is not applicable and is not used in IOM-2 mode only enabled in PCM/microcontroller mode. X3-HW Selection of the PCM highway for transmitting conferencing ...
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PCMX4 PCM Transmit Register 4 H Bit 7 6 X4- HW This register is not applicable and is not used in IOM-2 mode only enabled in PCM/microcontroller mode. X4-HW Selection of the PCM highway for transmitting conferencing ...
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TSTR1 Test Register 1 H Bit 7 6 PD-AC- PD-AC Register setting is only active if bit TEST-EN in register LMCR1 is set to 1. PD-AC-PR AC-PREFI Power Down PD-AC- PD-AC- PD-AC-PO AC-POFI ...
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PD-OFHC Off-hook comparator (OFHC) Power Down PD-OFHC = 0 PD-OFHC = 1 PD-OVTC Overtemperature comparator (OVTC) Power Down PD-OVTC = 0 PD-OVTC = 1 Preliminary Data Sheet Normal operation. Power Down mode. Normal operation. Power Down mode. 198 DuSLIC DS3, ...
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TSTR2 Test Register 2 H Bit 7 6 PD-DC Register setting is only active if bit TEST-EN in register LMCR1 is set to 1. PD-DC-PR DC-PREFI Power Down PD-DC- PD-DC- PD-DC-AD DC-ADC Power ...
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TSTR3 Test Register 3 H Bit Register setting is only active if bit TEST-EN in register LMCR1 is set to 1. AC-DLB-4M AC digital loop via a 4-MHz bitstream. (Loop encloses all digital hardware in ...