PEB 4364 T V1.2 Infineon Technologies, PEB 4364 T V1.2 Datasheet - Page 361

• Manufacturer Part Number: PEB 4364 T V1.2
• Description: IC SLIC VOICE ACCESS PDSO-36
• Manufacturer: Infineon Technologies
• Series: DuSLICr

Specifications of PEB 4364 T V1.2

• Function: Dual Channel Subscriber Line Interface Circuit (DuSLIC)
• Interface: IOM-2, PCM
• Number Of Circuits: 2
• Voltage - Supply: 3.3 V ~ 5 V
• Current - Supply: 105mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-PDSO
• Includes: DTMF Generator and Decoder, Line Echo Cancellation (LEC), Teletax (TTX) Generation, Universal Tone Detection (UTD)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB4364TV1.2XT; SP000007728

In the circuits shown in
and Ring lines. Longitudinal influence is cancelled out. This circuit therefore is
recommended for long line applications.
7.3
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Preliminary Data Sheet
For each of the supply pins of SLICOFI-2x and SLIC, 100 nF capacitors should be
used. These capacitors should be placed as close as possible to the supply pin of the
associated ground/supply pins.
SLICOFI-2x and SLIC should be placed as close to each other as possible.
SLICOFI-2x and SLIC should be placed in such way that lines ACP, ACN, DCP,
DCN, IT, ITAC are as short as possible.
ACP/ACN lines should be placed in parallel and symmetrical; connections via holes
should be avoided.
ACP/ACN lines should be run above a GND plane;
DCP/DCN lines should be placed in parallel and symmetrical; connections via holes
should be avoided.
DCP/DCN lines should be run above a GND plane
VCMITA and VCM should be connected directly (VCMITA via
R
VCMITB and VCM should be connected directly (VCMITB via
R
Use separate traces for connecting VCM/VCMITA and VCM/VCMITB;
these two VCM traces should be connected directly at the VCM pin of SLICOFI-2x
In case of a multilayer board, it is recommended to use one common ground layer
(AGND, BGND, GNDD, GNDA, GNDB, GNDPLL connected together and share one
ground layer).
In case of a two-layer board, a common ground should be used for AGND, BGND,
GNDD, GNDA, GNDB and GNDPLL. Ground traces should be laid out as large as
possible. Connections to and from ground pins should be as short as possible. Any
unused area of the board should be filled with ground (copper pouring).
The connection of GND,
impedance in order to avoid such issues as a GND shift due to the high impulse
currents in case of an overvoltage strike.
Tip/ring traces from the SLIC should be symmetrical.
IT2A
IT2B
(680 ).
(680 ).
DuSLIC Layout Recommendations
Figure 94
V
H
and
and
Figure 95
V
BAT
361
to the protection devices should be low-
the ring current is sensed in both Tip
Application Circuits
C
C
VCMITA
VCMITB
DS3, 2003-07-11
) at resistor
) at resistor
DuSLIC