PEB 4364 T V1.2 Infineon Technologies, PEB 4364 T V1.2 Datasheet - Page 11

• Manufacturer Part Number: PEB 4364 T V1.2
• Description: IC SLIC VOICE ACCESS PDSO-36
• Manufacturer: Infineon Technologies
• Series: DuSLICr

Specifications of PEB 4364 T V1.2

• Function: Dual Channel Subscriber Line Interface Circuit (DuSLIC)
• Interface: IOM-2, PCM
• Number Of Circuits: 2
• Voltage - Supply: 3.3 V ~ 5 V
• Current - Supply: 105mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-PDSO
• Includes: DTMF Generator and Decoder, Line Echo Cancellation (LEC), Teletax (TTX) Generation, Universal Tone Detection (UTD)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB4364TV1.2XT; SP000007728

List of Figures
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Preliminary Data Sheet
DuSLIC Chip Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Logic Symbol: SLICOFI-2/-2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Logic Symbol: SLIC-S/SLIC-S2 (V1.1, V1.2), SLIC-E/SLIC-E2 (V1.1) 26
Logic Symbol: SLIC-E/SLIC-E2 (V1.2) . . . . . . . . . . . . . . . . . . . . . . . . 26
Logic Symbol: SLIC-P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Logic Symbol: TSLIC-S/TSLIC-E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Line Circuit Functions in the DuSLIC-S/-S2 . . . . . . . . . . . . . . . . . . . . . 31
Line Circuit Functions in the DuSLIC-E/-E2/-P . . . . . . . . . . . . . . . . . . 31
Block Diagram: SLICOFI-2/-2S (PEB 3265, PEB 3264) . . . . . . . . . . . 32
Signal Paths – DC Feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DC Feeding Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Constant Current Zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Resistive Zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Constant Voltage Zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
TTX Voltage Reserve Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DC Feeding Characteristics (ACTH, ACTR) . . . . . . . . . . . . . . . . . . . . 41
Signal Paths – AC Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Signal Flow in Voice Channel (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Nyquist Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Typical Ringer Loads of 1 and 5 REN used in USA. . . . . . . . . . . . . . . 45
External Ringing Zero Crossing Synchronization . . . . . . . . . . . . . . . . 49
Balanced Ringing via SLIC-E/-E2, SLIC-S and SLIC-P. . . . . . . . . . . . 50
Unbalanced Ringing Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Teletax Injection and Metering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Soft Reversal (Example for Open Loop) . . . . . . . . . . . . . . . . . . . . . . . 55
DuSLIC AC Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
DuSLIC EDSP Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Bellcore On-Hook Caller ID Physical Layer Transmission . . . . . . . . . . 61
Line Echo Cancellation Unit Block Diagram . . . . . . . . . . . . . . . . . . . . 63
UTD Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
MWI Circuitry with Glow Lamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Conference Block for One DuSLIC Channel . . . . . . . . . . . . . . . . . . . . 69
DuSLIC Reset Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Reading Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Typical SLIC Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
DuSLIC Line Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Level Metering Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Single Measurement Sequence (AC & DC Level Metering) . . . . . . . . 97
Continuous Measurement Sequence (DC Level Metering) . . . . . . . . . 98
11
DS3, 2003-07-11
DuSLIC
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