PEB 4364 T V1.2 Infineon Technologies, PEB 4364 T V1.2 Datasheet - Page 100

• Manufacturer Part Number: PEB 4364 T V1.2
• Description: IC SLIC VOICE ACCESS PDSO-36
• Manufacturer: Infineon Technologies
• Series: DuSLICr

Specifications of PEB 4364 T V1.2

• Function: Dual Channel Subscriber Line Interface Circuit (DuSLIC)
• Interface: IOM-2, PCM
• Number Of Circuits: 2
• Voltage - Supply: 3.3 V ~ 5 V
• Current - Supply: 105mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-PDSO
• Includes: DTMF Generator and Decoder, Line Echo Cancellation (LEC), Teletax (TTX) Generation, Universal Tone Detection (UTD)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB4364TV1.2XT; SP000007728

3.8.2.5
The path of the DC level meter is shown in
will be determined and prepared depending on certain configuration settings. The
selected input signal becomes digitized after pre-filtering and analog-to-digital
conversion. The DC level meter is selected and enabled as shown in
Table 19
LM-SEL[3:0] in
register LMCR2
0100
0101
1001
1010
1011
1101
1110
1111
The effective sampling rate after the decimation stages is 2 kHz. The decimated value
has a resolution of 19 bits. The offset compensation value (see
the offset registers OFR1 (bits OFFSET-H[7:0]) and OFR2 (bits OFFSET-L[7:0]) can be
set to eliminate the offset caused by the SLIC current sensor, pre-filter, and analog-to-
digital converter. After the summation point the signal passes a programmable digital
gain filter. The additional gain factor is either 1 or 16 depending on register LMCR1 (bit
DC-AD16):
•
•
The rectifier after the gain filter can be turned on/off with:
•
•
A shift-factor K
integration operation to create an overflow. If an overflow in the level meter occurs, the
output result will be ± full scale (see
If the shift factor K
the integration result divided by 8.
Preliminary Data Sheet
LMCR1 (bit DC-AD16) = 0: No additional gain factor
LMCR1 (bit DC-AD16) = 1: Additional gain factor of 16
LMCR2 (bit LM-RECT) = 0: Rectifier disabled
LMCR2 (bit LM-RECT) = 1: Rectifier enabled
DC Level Metering
Selecting DC Level Meter Path
INTDC
INTDC
in front of the integrator prevents the level meter during an
DC Level Meter Path
DC out voltage on DCP-DCN
DC current on IT
DC current on IL
Voltage on IO3
Voltage on IO4
V
Offset of DC-pre-filter (short circuit on DC-pre-filter input)
Voltage on IO4 – IO3
is set to e.g. 1/8, the content of the level meter result register is
DD
Table
Figure
100
18).
40. Hereby, the DC level meter results
Operational Description
Chapter
Table
DS3, 2003-07-11
3.8.2.8) within
19:
DuSLIC