PEB 4364 T V1.2 Infineon Technologies, PEB 4364 T V1.2 Datasheet - Page 56

• Manufacturer Part Number: PEB 4364 T V1.2
• Description: IC SLIC VOICE ACCESS PDSO-36
• Manufacturer: Infineon Technologies
• Series: DuSLICr

Specifications of PEB 4364 T V1.2

• Function: Dual Channel Subscriber Line Interface Circuit (DuSLIC)
• Interface: IOM-2, PCM
• Number Of Circuits: 2
• Voltage - Supply: 3.3 V ~ 5 V
• Current - Supply: 105mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-PDSO
• Includes: DTMF Generator and Decoder, Line Echo Cancellation (LEC), Teletax (TTX) Generation, Universal Tone Detection (UTD)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB4364TV1.2XT; SP000007728

2.8
The signal processing capabilities described in this section are implemented by an
Enhanced Digital Signal Processor (EDSP), with the exception of DTMF generation.
Each function can be individually enabled or disabled for each DuSLIC channel.
Therefore, power consumption can be reduced according to the needs of the application.
For the MIPS requirements of the different EDSP algorithms see
Figure 28
matching loop, trans-hybrid filter, gain stages, and the connection to the EDSP.
Figure 28
Figure 29
signal names and SOP commands.
Figure 29
Preliminary Data Sheet
VOUT
VIN
+
IM1
+
TH
shows the AC signal path for DuSLIC with the ADCs and DACs, impedance
shows a close-up on the EDSP signal path shown in
DuSLIC Enhanced Signal Processing Capabilities
ADC
DAC
DAC
DuSLIC AC Signal Path
DuSLIC EDSP Signal Path
LPX
FRX
LPR
FRR
IM2
+
HPX1
AR1
AX1
+
TTXG
TTXA
G
L E C -X I
G
S
L E C ,T IN
IM3
LEC
G
S
S
L E C ,R
L E C ,T O U T
G
CID
HPX2
HPR2
TG
AR2
AX2
L E C -R I
+
L E C -O U T
G
L E C -X 0
G
LEC -EN
TH
56
+
LE C-E N
S
S U M
FRR
U TD X-S UM
LPX
FRX
LPR
U TD R
-S UM
D TM F-SR C
U TD X -S RC
HPX1
HPR1
AX1
AR1
UTDR -E N
G
UTDX -E N
D TM F
G
DuSLIC_0006_EDSPsignal_path
LEC
DTM F-EN
DuSLIC_0005_ACsignal_path
CID
TG
+
Functional Description
UTDX
DTMF
UTDR
CMP
EXP
Chapter
Figure 28
Switch
S
X O U T
S
R IN
x
R
Switch position
shown for control
bit set to 0
DS3, 2003-07-11
2.8.6.
identifying
DuSLIC
DTMF
UTD
UTD
CMP
EXP
EDSP
XOUT
RIN