PEB 4364 T V1.2 Infineon Technologies, PEB 4364 T V1.2 Datasheet - Page 88

• Manufacturer Part Number: PEB 4364 T V1.2
• Description: IC SLIC VOICE ACCESS PDSO-36
• Manufacturer: Infineon Technologies
• Series: DuSLICr

Specifications of PEB 4364 T V1.2

• Function: Dual Channel Subscriber Line Interface Circuit (DuSLIC)
• Interface: IOM-2, PCM
• Number Of Circuits: 2
• Voltage - Supply: 3.3 V ~ 5 V
• Current - Supply: 105mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-PDSO
• Includes: DTMF Generator and Decoder, Line Echo Cancellation (LEC), Teletax (TTX) Generation, Universal Tone Detection (UTD)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB4364TV1.2XT; SP000007728

3.6
Attention: Even if interrupts are not used in the system application, the user has
SLICOFI-2x provides extensive interrupt data for the host system. Interrupt handling is
performed by the on-chip microprogram that handles the interrupts in a fixed 2 kHz (500
SLICOFI-2x, depending on when the host reads the interrupt registers.
Independent of the selected interface mode (PCM/ C or IOM-2), the general behavior of
the interrupt is as follows:
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•
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3.6.1
When using SLICOFI-2, the following procedure has to be applied:
In case of an interrupt it is recommended to identify the interrupting channels first, before
reading all four interrupt registers (see
Preliminary Data Sheet
s) frame. Therefore, some delays up to 500 s can occur in the reactions of
Any change in one of the four interrupt registers (at some bits, only transitions from
0 to 1) leads to an interrupt. The interrupt channel bit INT-CH in INTREG1 is set to 1
and all interrupt registers of one DuSLIC channel are locked at the end of the interrupt
procedure (500 µs period). Therefore, all changes within one 2 kHz frame are stored
in the interrupt registers. The lock remains until the interrupt channel bit is cleared
(Release Interrupt by reading all four interrupt registers INTREG1 to INTREG4 with
one command).
In IOM-2 Interface mode, the interrupt channel bits are fed to the CIDU channel (see
IOM-CIDU). In PCM mode, the INT pin is set to active (low).
The interrupt is released (INT-CH bit reset to 0) by reading all four interrupt
registers by one command. Reading the interrupt registers one-by-one using a
series of commands does not release the interrupt even if all four registers are read.
A hardware or power-on reset of the chip clears all pending interrupts and resets the
INT line to inactive (PCM/µC mode) or resets the INT-CH bit in CIDU (IOM-2 mode).
The behavior after a software reset of both channels is similar, the interrupt signal
switches to non-active within 500 s. A software reset of one DuSLIC channel
deactivates the interrupt signal if there is no active interrupt on the other DuSLIC
channel.
If the reset line is deactivated, a reset interrupt is generated for each channel (bit
RSTAT in register INTREG2).
Interrupt Handling
to clear the reset interrupt after each power-up reset.
Recommended Procedure for Reading the Interrupt Registers
Figure
88
37):
Operational Description
DS3, 2003-07-11
DuSLIC