PEB 4364 T V1.2 Infineon Technologies, PEB 4364 T V1.2 Datasheet - Page 5

• Manufacturer Part Number: PEB 4364 T V1.2
• Description: IC SLIC VOICE ACCESS PDSO-36
• Manufacturer: Infineon Technologies
• Series: DuSLICr

Specifications of PEB 4364 T V1.2

• Function: Dual Channel Subscriber Line Interface Circuit (DuSLIC)
• Interface: IOM-2, PCM
• Number Of Circuits: 2
• Voltage - Supply: 3.3 V ~ 5 V
• Current - Supply: 105mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-PDSO
• Includes: DTMF Generator and Decoder, Line Echo Cancellation (LEC), Teletax (TTX) Generation, Universal Tone Detection (UTD)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB4364TV1.2XT; SP000007728

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Page 325
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Page 342
Page 344
Page 349
Table 35 "CRAM Coefficients" on Page
nibbles 6 and 7
“POP Command” on Page
programming added
“Sequence for POP Register Programming” on Page 207
(because added NLP coefficients)
“POP Register Overview” on Page
“POP Register Description” on Page
Table 53 "Range of DeltaPLEC" on Page
added.
Register CIS/LEC-MODE: description added for bit UTDX-SUM and note
on bit 3 added.
“Recommended NLP Coefficients” on Page 258
“SOP Command” on Page
Register XCR: Description for bit ASYNCH-R changed
Register LMRES1: bits added.
Register LMRES2: bits added.
Register BCR1: bits added.
Register DSCR, bit PTG: description added
Register LMCR1: bits added.
Register LMCR2: bits added.
Register LMCR3: bits added.
“COP Command” on Page
Table 73 "CRAM Coefficients" on Page
nibbles 6 and 7
“Electrical Characteristics” on Page
removed - for detailed information see device data sheets.
Table
AC Transmission Characteristics: Values for Distortion and associated
figures changed
“Input/Output Waveform for AC Tests” on Page 342
PCM interface timings
and
FSC hold time (t
FSC hold time 2 (t
time off (
IOM-2 interface timings
and
FSC hold time (t
FSC hold time 2 (t
Period PCLK (
“Double-Clocking Mode” on Page
“Double-Clocking Mode” on Page
76,
t
dTCoff
“AC Transmission” on Page
) modified
t
PCLK
FSC_h
FSC_h
FSC_h2
FSC_h2
) for double clocking: formula for typ. value modified.
) renamed to FSC hold time 1 (t
) renamed to FSC hold time 1 (t
“Single-Clocking Mode” on Page 344
) added, parameters and timing of pin DU modified
) added, formula of max. value for TCA/B delay
“Single-Clocking Mode” on Page 349
207: note on the necessity of immediate
266: note on empty register bits added
315: note on empty register bits added
208: NLP coefficients added
325: SLIC and SLICOFI-2x data
213: NLP coefficients added
326: Symbol V
346:
351:
205: TTX Slope extended by
318: TTX slope extended by
233: "0x80 - no detection"
added
FSC_h1
FSC_h1
RT
added.
renamed to V
),
),
added
TR