PEB 4364 T V1.2 Infineon Technologies, PEB 4364 T V1.2 Datasheet - Page 4

• Manufacturer Part Number: PEB 4364 T V1.2
• Description: IC SLIC VOICE ACCESS PDSO-36
• Manufacturer: Infineon Technologies
• Series: DuSLICr

Specifications of PEB 4364 T V1.2

• Function: Dual Channel Subscriber Line Interface Circuit (DuSLIC)
• Interface: IOM-2, PCM
• Number Of Circuits: 2
• Voltage - Supply: 3.3 V ~ 5 V
• Current - Supply: 105mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-PDSO
• Includes: DTMF Generator and Decoder, Line Echo Cancellation (LEC), Teletax (TTX) Generation, Universal Tone Detection (UTD)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB4364TV1.2XT; SP000007728

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“MIPS Requirements for EDSP Capabilities” on Page 66
NLP examples.
“Three-party Conferencing in DuSLIC-E/-E2/-P” on Page
about Multi-party Conferencing added
“Hardware and Power On Reset” on Page
changed to 1.5 ms.
Figure 36 "DuSLIC Reset Sequence" on Page
changed.
Table
“Recommended Procedure for Reading the Interrupt Registers” on
Page 88
“Power Management and Operating Modes” on Page
dissipation values and description updated.
“Integrated Test and Diagnostic Functions (ITDF)” on Page
is now also available for SLICOFI-2S.
Figure 3.8.1.2 "DuSLIC Line Testing" on Page
testing capability modified.
“Using the Level Metering Integrator” on Page
added.
Figure
SLICOFI-2 Version 1.5 added.
Table 20 "KINTDC Setting Table" on Page
DuSLICOS settings added below.
“Capacitance Measurements” on Page
added at the end of the chapter.
“Line Capacitance Measurements Ring and Tip to GND” on Page
description of last list item in section "Calculating parameter values"
modified, description in table of section "Program Sequence" modified
Chapter
“TIP/RING Interface” on Page
sheets for detailed information.
“SOP Command” on Page
Register XCR: Description for bit ASYNCH-R changed
Register INTREG1, bits HOOK and GNDK: description changes
Register INTREG2: reset value changed from 20
RSTAT modified
Register BCR1, bit SLEEP-EN: note added
Register BCR2: description added fot bits UTDX-SRC and PDOT-DIS
Register BCR5, bit DTMF-SRC: description added
Register DSCR, bit PTG: description added
“COP Command” on Page
17,
44,
added.
4.2.3,
“Default DC and AC Values” on Page
“Timing LM-OK Bit” on Page
Operation with IOM-2 TE Devices (1.536 MHz)
144: note on empty register bits added
203: note on empty register bits added
139: content removed - see device data
113: note on offset calibration
99: 1 ms delay time for
84: reset routine duration
101: description about
H
85: textual description
to 4F
94: description on line
97: timing for LM-OK bit
86: L
H
, description for bit
X
and L
90: Power
updated with
68: sentence
R
94: ITDF
changed.
added.
116: