PEB 4364 T V1.2 Infineon Technologies, PEB 4364 T V1.2 Datasheet - Page 68

• Manufacturer Part Number: PEB 4364 T V1.2
• Description: IC SLIC VOICE ACCESS PDSO-36
• Manufacturer: Infineon Technologies
• Series: DuSLICr

Specifications of PEB 4364 T V1.2

• Function: Dual Channel Subscriber Line Interface Circuit (DuSLIC)
• Interface: IOM-2, PCM
• Number Of Circuits: 2
• Voltage - Supply: 3.3 V ~ 5 V
• Current - Supply: 105mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-PDSO
• Includes: DTMF Generator and Decoder, Line Echo Cancellation (LEC), Teletax (TTX) Generation, Universal Tone Detection (UTD)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB4364TV1.2XT; SP000007728

The glow lamp circuit also requires a resistor (R
phone. When activated, the lamp must be able to either blink or remain on constantly.
In non-DuSLIC-E/-E2/-P solutions, the telephone ringer may respond briefly if the signal
slope is too steep; behavior that is not desirable. The integrated ramp generator of the
DuSLIC-E/-E2/-P can be programmed to increase the voltage slowly, to ensure that the
lamp is activated and not the ringer.
To activate the Message Waiting function of DuSLIC-E/-E2/-P, the following steps
should be performed:
1. Activating Ring Pause mode by setting the M0-M2 bits
2. Select Ring Offset RO2 by setting the bits in register LMCR3
3. Enable the ramp generator by setting bit RAMP-EN in register LMCR2
4. Switch between the Ring Offsets RO3 and RO2 in register LMCR3 to flash the lamp
The values for RO2 and RO3 must first be programmed in the CRAM to the appropriate
values so that the lamp will flash on and off.
Figure 34
2.10
Each DuSLIC-E/-E2/-P channel has a three-party conferencing facility implemented
which consist of four PCM registers, adders and gain stages in the microprogram and
the corresponding control registers (see
channels allows Multi-party Conferencing as well.
Preliminary Data Sheet
on and off (see
V
Three-party Conferencing in DuSLIC-E/-E2/-P
LOW
V
HIGH
10
11
Timing Diagram
Power Down
State
RNG-OFFSET Bits
V
TR
Figure
Lamp On
34).
Ring Pause
State
68
Figure
MW
) and a lamp (MW Lamp) built into the
35). Cascading DuSLIC-E/-E2/-P
Lamp Off
Functional Description
RO 3
RO 2
DS3, 2003-07-11
ezm14067
t
t
DuSLIC