MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 71

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

4.5.2 Highest Priority I Interrupt Register
Read: Anytime
Write: Only if I bit in CCR = 1 (interrupts inhibited)
To give a maskable interrupt source highest priority, write the low byte of the vector address to the HPRIO
register. For example, writing $F0 to HPRIO assigns highest maskable interrupt priority to the real-time
interrupt timer ($FFF0). If an unimplemented vector address or a non-I-masked vector address (a value
higher than $F2) is written, then IRQ is the default highest priority interrupt.
4.6 Resets
There are four possible sources of reset. POR and external reset on the RESET pin share the normal
reset vector. COP reset and the clock monitor reset each has a vector. Entry into reset is asynchronous
and does not require a clock, but the MCU cannot sequence out of reset without a system clock.
4.6.1 Power-On Reset (POR)
A positive transition on V
circuits are the usual source of reset in a system. The POR circuit only initializes internal circuitry during
cold starts and cannot be used to force a reset as system voltage drops.
4.6.2 External Reset
The CPU distinguishes between internal and external reset conditions by sensing whether the reset pin
rises to a logic 1 in less than eight E-clock cycles after an internal device releases reset. When a reset
condition is sensed, the RESET pin is driven low by an internal device for about 16 E-clock cycles, then
released. Eight E-clock cycles later it is sampled. If the pin is still held low, the CPU assumes that an
external reset has occurred. If the pin is high, it indicates that the reset was initiated internally by either
the COP system or the clock monitor.
To prevent a COP or clock monitor reset from being detected during an external reset, hold the reset pin
low for at least 32 cycles. An external resistor-capacitor (RC) power-up delay circuit on the reset pin is not
recommended because circuit charge time can cause the MCU to misinterpret the type of reset that has
occurred.
4.6.3 Computer Operating Properly (COP) Reset
The MCU includes a COP system to help protect against software failures. When COP is enabled,
software must write $55 and $AA (in this order) to the COPRST register to keep a watchdog timer from
timing out. Other instructions may be executed between these writes. A write of any value other than $55
or $AA or software failing to execute the sequence properly causes a COP reset to occur.
Freescale Semiconductor
Address:
Reset:
Read:
Write:
Figure 4-2. Highest Priority I Interrupt Register (HPRIO)
$001F
Bit 7
1
1
DD
causes a POR. An external voltage level detector or other external reset
6
1
1
M68HC12B Family Data Sheet, Rev. 9.1
PSEL5
5
1
PSEL4
4
1
PSEL3
3
0
PSEL2
2
0
PSEL1
1
1
Bit 0
0
0
Resets
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