MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 125

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Chapter 11
Pulse-Width Modulator (PWM)
11.1 Introduction
The pulse-width modulator (PWM) subsystem provides four independent 8-bit PWM waveforms or two
16-bit PWM waveforms or a combination of one 16-bit and two 8-bit PWM waveforms. Each waveform
channel has a programmable period and a programmable duty cycle as well as a dedicated counter. A
flexible clock select scheme allows four different clock sources to be used with the counters. Each of the
modulators can create independent, continuous waveforms with software-selectable duty rates from 0
percent to 100 percent. The PWM outputs can be programmed as left-aligned outputs or center-aligned
outputs. See
Figure
11-1,
Figure
11-2, and
Figure
11-3.
The period and duty registers are double buffered so that if they change while the channel is enabled, the
change does not take effect until the counter rolls over or the channel is disabled. If the channel is not
enabled, then writes to the period and/or duty register go directly to the latches as well as the buffer, thus
ensuring that the PWM output is always either the old waveform or the new waveform, not some variation
in between.
A change in duty or period can be forced into immediate effect by writing the new value to the duty and/or
period registers and then writing to the counter. This causes the counter to reset and the new duty and/or
period values to be latched. In addition, since the counter is readable it is possible to know where the
count is with respect to the duty value and software can be used to make adjustments by turning the
enable bit off and on.
The four PWM channel outputs share general-purpose port P pins. Enabling PWM pins takes precedence
over the general-purpose port. When PWM outputs are not in use, the port pins may be used for discrete
input/output.
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor
125