MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 70

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Resets and Interrupts
4.4 Latching of Interrupts
XIRQ is always level triggered and IRQ can be selected as a level-triggered interrupt. These
level-triggered interrupt pins should be released only during the appropriate interrupt service routine.
Generally, the interrupt service routine will handshake with the interrupting logic to release the pin. In this
way, the MCU will never start the interrupt service sequence only to determine that there is no longer an
interrupt source. In the event that this does occur, the trap vector will be taken.
If IRQ is selected as an edge-triggered interrupt, the hold time of the level after the active edge is
independent of when the interrupt is serviced. As long as the minimum hold time is met, the interrupt will
be latched inside the MCU. In this case, the IRQ edge interrupt latch is cleared automatically when the
interrupt is serviced.
All of the remaining interrupts are latched by the MCU with a flag bit. These interrupt flags should be
cleared during an interrupt service routine or when the interrupts are masked by the I bit. By doing this,
the MCU will never get an unknown interrupt source and take the trap vector.
4.5 Interrupt Control and Priority Registers
This section describes the interrupt control and priority registers.
4.5.1 Interrupt Control Register
Read: Anytime
Write: Varies from bit to bit
IRQE — IRQ Edge-Sensitive Only Bit
IRQEN — External IRQ Enable Bit
DLY — Oscillator Startup Delay on Exit from Stop Mode Bit
70
IRQE can be written once in normal modes. In special modes, IRQE can be written anytime, but the
first write is ignored.
IRQEN can be written anytime in all modes. The IRQ pin has an internal pullup.
DLY can be written once in normal modes. In special modes, DLY can be written anytime.
The delay time of about 4096 cycles is based on the E-clock rate.
1 = IRQ pin responds only to falling edges.
0 = IRQ pin responds to low levels.
1 = IRQ pin connected to interrupt logic
0 = IRQ pin disconnected from interrupt logic
1 = Stabilization delay on exit from stop mode
0 = No stabilization delay on exit from stop mode
Address: $001E
Reset:
Read:
Write:
IRQE
Bit 7
0
Figure 4-1. Interrupt Control Register (INTCR)
IRQEN
6
1
M68HC12B Family Data Sheet, Rev. 9.1
DLY
5
1
4
0
0
3
0
0
2
0
0
1
0
0
Freescale Semiconductor
Bit 0
0
0