MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 102

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

FLASH EEPROM
8.3.4 FLASH EEPROM Control Register
This register controls the programming and erasure of the FLASH EEPROM.
FEESWAI — FLASH EEPROM Stop in Wait Control Bit
SVFP — Status V
ERAS — Erase Control Bit
LAT — Latch Control Bit
ENPE — Enable Programming/Erase Bit
102
SVFP is a read-only bit.
This bit can be read anytime or written when ENPE = 0. When set, all locations in the array will be
erased at the same time. The boot block will be erased only if BOOTP = 0. This bit also affects the
result of attempted array reads. See
ENPE is set.
This bit can be read anytime or written when ENPE = 0. When set, the FLASH EEPROM is configured
for programming or erasure and, upon the next valid write to the array, the address and data will be
latched for the programming sequence. See
voltage detect circuit on the V
is at normal levels.
ENPE can be asserted only after LAT has been asserted and a write to the data and address latches
has occurred. If an attempt is made to assert ENPE when LAT is negated, or if the latches have not
been written to after LAT was asserted, ENPE will remain negated after the write cycle is complete.
The LAT, ERAS, and BOOTP bits cannot be changed when ENPE is asserted. A write to FEECTL may
affect only the state of ENPE. Attempts to read a FLASH EEPROM array location in the FLASH
EEPROM module while ENPE is asserted will not return the data addressed. See
information.
0 = Do not halt FLASH EEPROM clock when in wait mode.
1 = Halt FLASH EEPROM clock when in wait mode.
0 = Voltage of V
1 = Voltage of V
0 = FLASH EEPROM configured for programming
1 = FLASH EEPROM configured for erasure
0 = Programming latches disabled
1 = Programming latches enabled
0 = Disables program/erase voltage to FLASH EEPROM
1 = Applies program/erase voltage to FLASH EEPROM
The FEESWAI bit cannot be asserted if the interrupt vector resides in the
FLASH EEPROM array.
Address: $00F7
Reset:
Read:
Write:
FP
Voltage Bit
FP
FP
Figure 8-4. FLASH EEPROM Control Register (FEECTL)
pin is below normal programming voltage levels.
pin is above normal programming voltage levels.
Bit 7
0
0
FP
pin will prevent assertion of the LAT bit when the programming voltage
M68HC12B Family Data Sheet, Rev. 9.1
6
0
0
Table 8-1
5
0
0
Table 8-1
NOTE
for more information. Status of ERAS cannot change if
FEESWAI
4
0
for the effects of LAT on array reads. A high
SVFP
3
0
ERAS
2
0
LAT
1
0
Freescale Semiconductor
Table 8-1
ENPE
Bit 0
0
for more