MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 28

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

General Description
1.6.3.2 ECLK
ECLK is the output connection for the internal bus clock and is used to demultiplex the address and data
and is used as a timing reference. ECLK frequency is equal to one half the crystal frequency out of reset.
In normal single-chip mode, the E-clock output is off at reset to reduce the effects of radio frequency
interference (RFI), but it can be turned on if necessary.
In special single-chip mode, the E-clock output is on at reset but can be turned off.
In special peripheral mode, the E clock is an input to the MCU.
All clocks, including the E clock, are halted when the MCU is in stop mode. It is possible to configure the
MCU to interface to slow external memory. ECLK can be stretched for such accesses.
1.6.3.3 RESET
An active-low, bidirectional control signal, RESET is an input to initialize the MCU to a known startup
state. It also acts as an open-drain output to indicate that an internal failure has been detected in either
the clock monitor or COP watchdog circuit. The MCU goes into reset asynchronously and comes out of
reset synchronously. This allows the part to reach a proper reset state even if the clocks have failed, while
allowing synchronized operation when starting out of reset.
It is possible to determine whether a reset was caused by an internal source or an external source. An
internal source drives the pin low for 16 cycles; eight cycles later, the pin is sampled. If the pin has
returned high, either the COP watchdog vector or clock monitor vector is taken. If the pin is still low, the
external reset is determined to be active and the reset vector is taken. Hold reset low for at least 32 cycles
to assure that the reset vector is taken in the event that an internal COP watchdog timeout or clock monitor
fail occurs.
1.6.3.4 IRQ
IRQ is the maskable external interrupt request pin. It provides a means of applying asynchronous interrupt
requests to the MCU. Either falling edge-sensitive triggering or level-sensitive triggering is program
28
MCU
Figure 1-6. External Oscillator Connections
MCU
Figure 1-5. Common Crystal Connections
EXTAL
XTAL
EXTAL
XTAL
M68HC12B Family Data Sheet, Rev. 9.1
NC
10 MΩ
EXTERNAL OSCILLATOR
CMOS-COMPATIBLE
CRYSTAL
2 x E
2 x E
C
C
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