MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 116

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Clock Generation Module (CGM)
10.5 Slow Mode Divider
The slow mode divider is included to deliver a variable bus frequency to the MCU in wait mode. The bus
clocks are derived from the constant P clock. The slow clock counter divides the P clock and E clock
frequency in powers of 2, up to 128. When the slow control register is cleared or the part is not in wait
mode, the slow mode divider is off and the bus clock’s frequency is not changed.
10.6 Clock Functions
The CGM generates and controls the timing of the reset and POR logic.
10.6.1 Computer Operating Properly (COP)
The computer operating properly (COP) or watchdog timer is an added check that a program is running
and sequencing properly. When the COP is being used, software is responsible for keeping a free-running
watchdog timer from timing out. If the watchdog timer times out, it is an indication that the software is no
longer being executed in the intended sequence; thus, a system reset is initiated. Three control bits allow
selection of seven COP timeout periods or COP disable. When COP is enabled, sometime during the
selected period the program must write $55 and $AA (in this order) to the arm/reset COP register
(COPRST). If the program fails to do this, the part resets. If any value other than $55 or $AA is written to
COPRST, the part is reset.
10.6.2 Real-Time Interrupt
There is a real-time (periodic) interrupt available to the user. This interrupt occurs at one of seven selected
rates. An interrupt flag and an interrupt enable bit are associated with this function. There are three bits
for the rate select.
10.6.3 Clock Monitor
The clock monitor circuit is based on an internal resistor-capacitor (RC) time delay. If no MCU clock edges
are detected within this RC time delay, the clock monitor can optionally generate a system reset. The
clock monitor function is enabled/disabled by the CME control bit in the COP control register (COPCTL).
This timeout is based on an RC delay so that the clock monitor can operate without any MCU clocks.
Clock monitor timeouts are shown in
116
The clock monitor is clocked by the system clock (oscillator) reference; the
slow mode divider allows operation of the MCU at clock periods longer than
the clock monitor trigger time.
5 V ± 10%
Table 10-1. Clock Monitor Timeout
Supply
M68HC12B Family Data Sheet, Rev. 9.1
Table
10-1.
NOTE
2–20 µs
Range
Freescale Semiconductor