MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 153

MC68HC912B32VFU8

Manufacturer Part Number
MC68HC912B32VFU8
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68HC912B32VFU8

Cpu Family
HC12
Device Core Size
16b
Frequency (max)
8MHz
Interface Type
SCI/SPI
Program Memory Type
EPROM
Program Memory Size
32KB
Total Internal Ram Size
1KB
# I/os (max)
63
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC912B32VFU8
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
12.3.11 Pulse Accumulator Flag Register
Read: Anytime
Write: Anytime
When the TFFCA bit in the TSCR register is set, any access to the PACNT register clears all the flags in
the PAFLG register.
PAOVF — Pulse Accumulator Overflow Flag
PAIF — Pulse Accumulator Input Edge Flag
12.3.12 16-Bit Pulse Accumulator Count Register
Read: Anytime
Write: Anytime
Full count register access should take place in one clock cycle. A separate read/write for high byte and
low byte will give a different result than accessing them as a word.
Freescale Semiconductor
Set when the 16-bit pulse accumulator overflows from $FFFF to $0000. This bit is cleared
automatically by a write to the PAFLG register with bit 1 set.
Set when the selected edge is detected at the pulse accumulator input pin. In event mode, the event
edge triggers PAIF. In gated time accumulation mode, the trailing edge of the gate signal at the pulse
accumulator input pin triggers PAIF. This bit is cleared automatically by a write to the PAFLG register
with bit 0 set.
Address: $00A1
Address: $00A2
Address: $00A3
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
Figure 12-26. 16-Bit Pulse Accumulator Count Register (PACNT)
Figure 12-25. Pulse Accumulator Flag Register (PAFLG)
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
0
0
0
0
Bit 14
Bit 6
6
0
0
6
0
6
0
M68HC12B Family Data Sheet, Rev. 9.1
Bit 13
Bit 5
5
0
0
5
0
5
0
Bit 12
Bit 4
4
0
0
4
0
4
0
Bit 11
Bit 3
3
0
0
3
0
3
0
Bit 10
Bit 2
2
0
0
2
0
2
0
PAOVF
Bit 9
Bit 1
1
0
1
0
1
0
PAIF
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0
0
0
0
Block Diagram
153

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