MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 152

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Standard Timer (TIM)
PAEN — Pulse Accumulator System Enable Bit
PAMOD — Pulse Accumulator Mode Bit
PEDGE — Pulse Accumulator Edge Control Bit
CLK1 and CLK0 — Clock Select Bits
PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit
PAI — Pulse Accumulator Input Interrupt Enable Bit
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PAEN is independent from TEN.
For PAMOD = 0 (event counter mode)
For PAMOD = 1 (gated time accumulation mode)
If the timer is not active (TEN = 0 in TSCR), there is no ÷64 clock since the E ÷ 64 clock is generated
by the timer prescaler.
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as
an input clock to the timer counter. The change from one selected clock to the other happens
immediately after these bits are written.
0 = Pulse accumulator system disabled
1 = Pulse accumulator system enabled
0 = Event counter mode
1 = Gated time accumulation mode
0 = Falling edges on the pulse accumulator input pin (PT7/PAI) cause the count to be incremented.
1 = Rising edges on the pulse accumulator input pin cause the count to be incremented.
0 = Pulse accumulator input pin high enables E ÷ 64 clock to pulse accumulator and the trailing
1 = Pulse accumulator input pin low enables E ÷ 64 clock to pulse accumulator and the trailing rising
0 = Interrupt inhibited
1 = Interrupt requested if PAOVF is set
0 = Interrupt inhibited
1 = Interrupt requested if PAIF is set
falling edge on the pulse accumulator input pin sets the PAIF flag.
edge on the pulse accumulator input pin sets the PAIF flag.
CLK1
0
0
1
1
CLK0
0
1
0
1
M68HC12B Family Data Sheet, Rev. 9.1
Use timer prescaler clock as timer counter clock
Use PACLK as input to timer counter clock
Use PACLK/256 as timer counter clock frequency
Use PACLK/65536 as timer counter clock frequency
Table 12-4. Clock Selection
Selected Clock
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