MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 41

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
Addr.
$001D
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$001E
$001F
$0020
Notes:
↓
1. Available only on MC68HC912B32 and MC68HC912BC32 devices.
2. Available only on MC68HC912B32 and MC68HC12BE32 devices.
3. Available only on MC68HC(9)12BC32 devices.
Highest Priority I Interrupt Register
Real-Time Interrupt Flag Register
Miscellaneous Mapping Control
EEPROM Initialization Register
Register Initialization Register
Breakpoint Control Register 0
Real-Time Interrupt Control
Register Name
RAM Initialization Register
Interrupt Control Register
Arm/Reset COP Timer
COP Control Register
Register (COPRST)
Register (RTICTL)
Register (MISC)
See page 118.
See page 119.
See page 119.
See page 120.
See page 301.
See page 80.
See page 80.
See page 81.
See page 82.
See page 70.
See page 71.
(COPCTL)
(BRKCT0)
Reserved
Reserved
(RTIFLG)
(INITRM)
(INITRG)
(INITEE)
(HPRIO)
(INTCR)
Figure 2-1. Register Map (Sheet 2 of 19)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
M68HC12B Family Data Sheet, Rev. 9.1
RAM15
REG15
BKEN1
EE15
IRQE
RTIE
RTIF
CME
Bit 7
Bit 7
R
R
0
0
0
0
0
0
0
0
0
0
1
1
0
= Unimplemented
RAM14
REG14
RSWAI
IRQEN
BKEN0
NDRF
FCME
EE14
Bit 6
R
R
6
0
0
0
0
0
0
0
0
0
1
1
1
0
RFSTR1
RAM13
RSBCK
REG13
PSEL5
BKPM
EE13
FCM
Bit 5
DLY
R
R
5
0
0
0
0
0
0
0
0
0
1
1
0
RFSTR0
RAM12
REG12
PSEL4
FCOP
EE12
Bit 4
R
R
R
4
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
= Reserved
EXSTR1
BK1ALE
RAM11
REG11
RTBYP
PSEL3
DISR
Bit 3
R
R
3
1
0
0
0
0
0
0
0
0
0
0
0
0
0
EXSTR0
BK0ALE
PSEL2
RTR2
CR2
Bit 2
R
R
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
U = Unaffected
MAPROM
PSEL1
RTR1
CR1
Bit 1
R
R
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Registers
MMSWAI
ROMON
EEON
RTR0
Bit 0
CR0
Bit 0
R
R
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
41