MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 53

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
Addr.
$00DC
$00D2
$00D3
$00D4
$00D5
$00D6
$00D7
$00D8
$00DA
$00DB
$00DF
$00EF
$00E0
$00E1
$00F0
Notes:
↓
↓
↓
1. Available only on MC68HC912B32 and MC68HC912BC32 devices.
2. Available only on MC68HC912B32 and MC68HC12BE32 devices.
3. Available only on MC68HC(9)12BC32 devices.
EEPROM Configuration Register
Port S Data Direction Register
Port S Pullup/Reduced Drive
Slow Mode Divider Register
Register Name
SPI Baud Rate Register
Port S Data Register
SPI Status Register
Register (PURDS)
SPI Data Register
See page 206.
See page 207.
See page 207.
See page 208.
See page 208.
See page 209.
See page 117.
See page 94.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
(EEMCR)
(PORTS)
(SP0BR)
(SP0SR)
(SP0DR)
(SLOW)
(DDRS)
Figure 2-1. Register Map (Sheet 14 of 19)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
M68HC12B Family Data Sheet, Rev. 9.1
DDS7
SPIF
Bit 7
Bit 7
PS7
R
R
R
R
R
R
R
0
0
0
0
0
0
0
1
1
= Unimplemented
RDPS2
WCOL
DDS6
Bit 6
PS6
R
R
R
R
R
R
R
6
0
0
0
0
0
0
1
1
After reset all bits configured as general-purpose inputs
After reset all bits configured as general-purpose inputs
RDPS1
DDS5
Bit 5
PS5
R
R
R
R
R
R
R
5
0
0
0
0
0
0
0
1
1
RDPS0
Unaffected by reset
MODF
DDS4
Bit 4
PS4
R
R
R
R
R
R
R
R
4
0
0
0
0
0
0
1
1
= Reserved
DDS3
Bit 3
PS3
R
R
R
R
R
R
R
3
0
0
0
0
0
0
0
0
1
1
EESWAI
PUPS2
SLDV2
SPR2
DDS2
Bit 2
PS2
R
R
R
R
R
R
R
2
0
0
0
0
0
1
U = Unaffected
PROTLCK
PUPS1
SLDV1
DDS1
SPR1
Bit 1
PS1
R
R
R
R
R
R
R
1
0
0
0
0
0
0
Registers
PUPS0
SLDV0
EERC
SPR0
DDS0
Bit 0
Bit 0
PS0
R
R
R
R
R
R
R
0
0
0
0
0
0
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