MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 63

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

3.4 Data Types
The CPU12 supports four data types:
A byte is eight bits wide and can be accessed at any byte location. A word is composed of two consecutive
bytes with the most significant byte at the lower value address. There are no special requirements for
alignment of instructions or operands.
3.5 Addressing Modes
Addressing modes determine how the CPU accesses memory locations to be operated upon. The CPU12
includes all of the addressing modes of the M68HC11 CPU as well as several new forms of indexed
addressing.
Freescale Semiconductor
auto post-increment
auto pre-decrement
Addressing Mode
auto pre-increment
1. Bit data
2. 8-bit and 16-bit signed and unsigned integers
3. 16-bit unsigned fractions
4. 16-bit addresses
accumulator offset
16-bit offset
Immediate
5-bit offset
decrement
9-bit offset
auto post-
Extended
Inherent
Relative
Indexed
Indexed
Indexed
Indexed
Indexed
Indexed
Indexed
Indexed
Direct
Table 3-1
is a summary of the available addressing modes.
INST oprx16,xysp
INST oprx5,xysp
INST oprx3,–xys
INST oprx3,+xys
INST oprx3,xys–
INST oprx3,xys+
INST oprx9,xysp
Source Format
INST abd,xysp
INST #opr16i
INST opr16a
INST #opr8i
INST opr8a
INST rel16
INST rel8
INST
or
or
Table 3-1. Addressing Mode Summary
M68HC12B Family Data Sheet, Rev. 9.1
Abbreviation
IDX1
IDX2
IMM
EXT
REL
INH
DIR
IDX
IDX
IDX
IDX
IDX
IDX
Operands (if any) are in CPU registers.
Operand is included in instruction stream
8- or 16-bit size implied by context.
Operand is the lower 8 bits of an address in the range
$0000–$00FF.
Operand is a 16-bit address.
An 8-bit or 16-bit relative offset from the current pc is
supplied in the instruction.
5-bit signed constant offset from x, y, sp, or pc
Auto pre-decrement x, y, or sp by 1 ~ 8
Auto pre-increment x, y, or sp by 1 ~ 8
Auto post-decrement x, y, or sp by 1 ~ 8
Auto post-increment x, y, or sp by 1 ~ 8
Indexed with 8-bit (A or B) or 16-bit (D) accumulator
offset from x, y, sp, or pc
9-bit signed constant offset from x, y, sp, or pc
(lower 8 bits of offset in one extension byte)
16-bit constant offset from x, y, sp, or pc
(16-bit offset in two extension bytes)
Description
Table continued on next page
Data Types
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