MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 248

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

248
msCAN12 Controller
2. Four identifier acceptance filters, each to be applied to:
3. Eight identifier acceptance filters, each to be applied to the first eight bits of the identifier. This
4. Closed filter. No CAN message will be copied into the foreground buffer RxFG, and the RXF flag
Figure 16-4
filter 0 and 1 hit. Similarly, the second filter bank (CIDAR4–CUIDAR7, CIDMR4–CIDMR7)
produces filter 2 and three hits.
mode implements eight independent filters for the first eight bits of a CAN 2.0A compliant standard
identifier or of a CAN 2.0B compliant extended identifier.
bank (CIDAR0–CIDAR3, CIDMR0–CIDMR3) produces filter 0 to three hits. Similarly, the second
filter bank (CIDAR4–CUIDAR7, CIDMR4–CIDMR7) produces filter 4 to seven hits.
will never be set.
a. 11 bits of the identifier and the RTR bit of CAN 2.0A messages, or
b. 14 most significant bits of the identifier of CAN 2.0B messages
ID28
ID10
AC7
AC7
AC7
AC7
shows how the first 32-bit filter bank (CIDAR0–CIDAR3, CIDMR0–CIDMR3) produces
CIDMRO
CIDARO
CIDMR2
CIDAR2
IDR0
IDR0
ID accepted (Filter 0 hit)
ID accepted (Filter 1 hit)
Figure 16-4. 16-Bit Maskable Acceptance Filters
ID21 ID20
AC0 AC7
AC0 AC7
AC0 AC7
AC0 AC7
ID3 ID2
M68HC12B Family Data Sheet, Rev. 9.1
CIDMR1
CIDMR3
CIDAR1
CIDAR3
IDR1
IDR1
IDE
ID15 ID14
AC0
AC0
AC0
AC0
IDR2
Figure 16-5
ID7
ID6
shows how the first 32-bit filter
IDR3
RTR
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