MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 285

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

CC2–CC0 — Conversion Counter Bits for Current 4 or 8 Conversions
CCF7–CCF0 — Conversion Complete Flags
17.3.8 ATD Test Registers
Read: Special modes only
Write: Special modes only
The test registers control various special modes which are used during manufacturing. In the normal
modes, reads of the test register return 0 and writes have no effect.
SAR9–SAR0 — SAR Data Bits
RST — Module Reset Bit
TSTOUT — Multiplex Output of TST3–TST0 (Factory Use)
TST3–TST0 — Test Bits 3 to 0 (Reserved)
Freescale Semiconductor
This 3-bit value reflects the contents of the conversion counter pointer in a four or eight count
sequence. This value also reflects which result register is written next, indicating which channel is
currently being converted.
Each CCF bit is associated with an individual ATD result register. For each register, this bit is set at
the end of conversion for the associated ATD channel and remains set until that ATD result register is
read. It is cleared at that time if AFFC bit is set, regardless of whether a status register read has been
performed (for example, a status register read is not a pre-qualifier for the clearing mechanism when
AFFC = 1). Otherwise, the status register must be read to clear the flag.
Reads of this byte return the current value in the SAR. Writes to this byte change the SAR to the value
written. Bits SAR9–SAR0 reflect the 10 SAR bits used during the resolution process for an 10-bit result.
When set, this bit causes all registers and activity in the module to assume the same state as out of
power-on reset (except for ADPU bit in ATDCTL2, which remains set, allowing the ATD module to
remain enabled).
Selects one of 16 reserved factory testing modes
Address: $0068
Address: $0069
Reset:
Reset:
Read:
Read:
Write:
Write:
SAR9
SAR1
Bit 7
Bit 7
0
0
Figure 17-11. ATD Test Register (ATDSTAT)
SAR8
SAR0
6
0
6
0
M68HC12B Family Data Sheet, Rev. 9.1
SAR7
RST
5
0
5
0
Figure 17-10
TSTOUT
SAR6
4
0
4
0
SAR5
TST3
3
0
3
0
SAR4
TST2
2
0
2
0
SAR3
TST1
1
0
1
0
SAR2
TST0
Bit 0
Bit 0
0
0
ATD Registers
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