MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 32

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

General Description
1.6.4 Port Signals
The MCU incorporates eight ports which are used to control and access the various device subsystems.
When not used for these purposes, port pins may be used for general-purpose I/O. In addition to the pins
described here, each port consists of:
After reset, all port pins are configured as input. (Refer to
descriptions.)
1.6.4.1 Port A
Port A pins are used for address and data in expanded modes. The port data register is not in the address
map during expanded and peripheral mode operation. When it is in the map, port A can be read or written
at anytime.
The port A data direction register (DDRA) determines whether each port A pin is an input or output. DDRA
is not in the address map during expanded and peripheral mode operation. Setting a bit in DDRA makes
32
Port A
PA7–PA0
Port B
PB7–PB0
Port AD
PAD7–PAD0
Port DLC/PCAN
PDLC6–PDLC0
PCAN6–PCAN2
Port E
PE7–PE0
Port P
PP7–PP0
Port S
PS7–PS0
Port T
PT7–PT0
1. Port DLC applies to the MC68HC912B32 and MC68HC12BE32 and PCAN to the MC68HC(9)12BC32.
•
•
Port Name
A data register which can be read and written at any time
With the exception of port AD and PE1–PE0, a data direction register which controls the direction
of each pin
(1)
26–29, 35–38
79, 80, 1–6
16–12, 9–7
Numbers
46–39
25–18
58–51
70–76
68–61
Pin
Table 1-4. Port Description Summary
DD Register (Address)
M68HC12B Family Data Sheet, Rev. 9.1
DDRDLC ($00FF)
PE7–PE2 In/Out
Data Direction
DDRS ($00D7)
DDRA ($0002)
DDRB ($0003)
DDRE ($0009)
DDRP ($0057)
DDRT ($00AF)
PE1–PE0 In
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In
Port A and port B pins are used for address and data in
expanded modes. The port data registers are not in the
address map during expanded and peripheral mode
operation. When in the map, port A and port B can be
read or written anytime.
DDRA and DDRB are not in the address map in
expanded or peripheral modes.
Analog-to-digital converter and general-purpose I/O
Byte data link communication (BDLC) subsystem and
general-purpose I/O
Mode selection, bus control signals, and interrupt
service request signals; or general-purpose I/O
General-purpose I/O. PP3–PP0 are used with the
pulse-width modulator when enabled.
Serial communications interface and serial peripheral
interface subsystems and general-purpose I/O
General-purpose I/O when not enabled for input capture
and output compare in the timer and pulse accumulator
subsystem
Table 1-4
for a summary of the port signal
Description
Freescale Semiconductor