MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 236

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Byte Data Link Communications (BDLC)
TMIFR0 — Transmit Multiple Byte IFR without CRC (Type 3)
TMIFR1 — Transmit Multiple Byte IFR with CRC Bit (Type 3)
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The TMIFR0 bit is used to request the BDLC to transmit the byte in the BDLC data register (BDR) as
the first byte of a multiple byte IFR without CRC. Response IFR bytes are still subject to J1850
message length maximums (see
If the TMIFR0 bit is set, the BDLC attempts to transmit the normalization symbol followed by the byte
in the BDR. After the byte in the BDR has been loaded into the transmit shift register, a TDRE interrupt
(see
programmer should then load the next byte of the IFR into the BDR for transmission. When the last
byte of the IFR has been loaded into the BDR, the programmer should set the TEOD bit in the BCR2.
This instructs the BDLC to transmit an EOD symbol once the byte in the BDR is transmitted, indicating
the end of the IFR portion of the message frame. The BDLC does not append a CRC when the TMIFR0
is set.
If the programmer attempts to set the TMIFR0 bit after the EOD symbol has been received from the
bus, the TMIFR0 bit remains in the reset state, and no attempt is made to transmit an IFR byte.
If a loss of arbitration occurs when the BDLC is transmitting, the TMIFR0 bit is cleared, and no attempt
is made to retransmit the byte in the BDR. If loss of arbitration occurs in the last bit of the IFR byte, two
additional 1 bits are sent out.
The TMIFR1 bit requests the BDLC to transmit the byte in the BDLC data register (BDR) as the first
byte of a multiple byte IFR with CRC or as a single byte IFR with CRC. Response IFR bytes are still
subject to J1850 message length maximums (see
1 = If set prior to a valid EOD being received with no CRC error, once the EOD symbol has been
0 = Bit is cleared automatically once the BDLC has successfully transmitted the EOD symbol, by
1 = If this bit is set prior to a valid EOD being received with no CRC error, once the EOD symbol
0 = The bit is cleared automatically, once the BDLC has successfully transmitted the CRC byte and
15.9.3 BDLC State Vector
received, the BDLC attempts to transmit the appropriate normalization bit followed by IFR
bytes. The programmer should set TEOD after the last IFR byte has been written into the BDR.
After TEOD has been set, the last IFR byte to be transmitted is the last byte which was written
into the BDR.
the detection of an error on the multiplex bus or by a transmitter underrun caused when the
programmer does not write another byte to the BDR after the TDRE interrupt.
has been received, the BDLC attempts to transmit the appropriate normalization bit followed
by IFR bytes. The programmer should set TEOD after the last IFR byte has been written into
the BDR. After TEOD has been set and the last IFR byte has been transmitted, the CRC byte
is transmitted.
EOD symbol, by the detection of an error on the multiplex bus or by a transmitter underrun
caused when the programmer does not write another byte to the BDR after the TDRE interrupt.
The extra logic 1 bits are an enhancement to the J1850 protocol which
forces a byte boundary condition fault. This is helpful in preventing noise
onto the J1850 bus from a corrupted message.
Register) occurs similar to the main message transmit sequence. The
M68HC12B Family Data Sheet, Rev. 9.1
15.7.2 J1850 Frame Format
NOTE
15.7.2 J1850 Frame Format
and
Figure
15-14).
and
Freescale Semiconductor
Figure
15-14).