MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 213

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Chapter 15
Byte Data Link Communications (BDLC)
15.1 Introduction
The byte data link communications module (BDLC) provides access to an external serial communication
multiplex bus, operating according to the SAE J1850 protocol.
15.2 Features
Features of the BDLC module include:
15.3 Functional Description
Figure 15-1
addressable registers and provides the link between the CPU and the buffers. The buffers provide storage
for data received and data to be transmitted onto the J1850 bus. The protocol handler is responsible for
the encoding and decoding of data bits and special message symbols during transmission and reception.
The MUX interface provides the link between the BDLC digital section and the analog physical interface.
The wave shaping, driving, and digitizing of data is performed by the physical interface.
Use of the BDLC module in message networking fully implements the SAE Standard J1850 Class B Data
Communication Network Interface specification.
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SAE J1850 Class B Data Communications Network Interface compatible and ISO compatible for
low-speed (<125 Kbps) serial data communications in automotive applications
10.4 Kbps variable pulse width (VPW) bit format
Digital noise filter
Collision detection
Hardware cyclical redundancy check generation and checking
Two power-saving modes with automatic wakeup on network activity
Polling or CPU interrupts
Block mode receive and transmit
4X receive mode, 41.6 Kbps
Digital loopback mode
Analog loopback mode
In-frame response (IFR) types 0, 1, 2, and 3
shows the organization of the BDLC module. The CPU interface contains the software
Familiarity with the SAE Standard J1850 Class B Data Communication
Network Interface specification is recommended before proceeding.
First-time users of the BDLC should obtain the Byte Data Link Controller
Reference Manual, Freescale document order number BDLCRM/AD.
M68HC12B Family Data Sheet, Rev. 9.1
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