MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 185

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

DDT[7:0] — Data Direction Bits for Timer Port
13.4.23 16-Bit Pulse Accumulator B Control Register
Read: Anytime
Write: Anytime
Sixteen-bit pulse accumulator B (PACB) is formed by cascading the 8-bit pulse accumulators PAC1 and
PAC0. When PBEN is set, the PACB is enabled. The PACB shares the input pin with IC0.
PBEN — Pulse Accumulator B System Enable Bit
PBOVI — Pulse Accumulator B Overflow Interrupt Enable Bit
13.4.24 Pulse Accumulator B Flag Register
Freescale Semiconductor
The timer forces the I/O state to be an output for each timer port line associated with an enabled output
compare. In these cases the data direction bits will not be changed, but have no effect on the direction
of these pins. The DDRT will revert to controlling the I/O direction of a pin when the associated timer
output compare is disabled. Input captures do not override the DDRT settings.
PBEN is independent from TEN. With timer disabled, the pulse accumulator can still function unless
pulse accumulator is disabled.
•
•
0 = Configures the corresponding I/O pin for input only
1 = Configures the corresponding I/O pin for output
0 = 16-bit pulse accumulator system disabled. Eight-bit PAC1 and PAC0 can be enabled when their
1 = Pulse accumulator B system enabled. The two 8-bit pulse accumulators PAC1 and PAC0 are
0 = Interrupt inhibited
1 = Interrupt requested if PBOVF is set
Read:Anytime
Write:Anytime
related enable bits in ICPACR ($A8) are set.
cascaded to form the PACB 16-bit pulse accumulator. When PACB is enabled, the PACN1 and
PACN0 register contents are, respectively, the high and low byte of the PACB. PA1EN and
PA0EN control bits in ICPACR ($A8) have no effect.
Address: $00B0
Address: $00B1
Reset:
Figure 13-44. 16-Bit Pulse Accumulator B Control Register (PBCTL)
Reset:
Read:
Read:
Write:
Write:
Figure 13-45. Pulse Accumulator B Flag Register (PBFLG)
Bit 7
Bit 7
0
0
0
0
PBEN
6
0
6
0
0
M68HC12B Family Data Sheet, Rev. 9.1
5
0
0
5
0
0
4
0
0
4
0
0
3
0
0
3
0
0
2
0
0
2
0
0
PBOVF
PBOV
1
0
1
0
Bit 0
Bit 0
0
0
0
0
Timer Registers
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