MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 179
MC68HC912B32VFU8
Manufacturer Part Number
MC68HC912B32VFU8
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68HC912B32VFU8.pdf
(334 pages)
Specifications of MC68HC912B32VFU8
Cpu Family
HC12
Device Core Size
16b
Frequency (max)
8MHz
Interface Type
SCI/SPI
Program Memory Type
EPROM
Program Memory Size
32KB
Total Internal Ram Size
1KB
# I/os (max)
63
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC912B32VFU8
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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The two 8-bit pulse accumulators, PAC1 and PAC0, are cascaded to form the PACB 16-bit pulse
accumulator. When PACB in enabled, (PBEN = 1 in PBCTL, $B0) the PACN1 and PACN0 register
contents are, respectively, the high and low bytes of the PACB.
When PACN1 overflows from $FF to $00, the interrupt flag PBOVF in PBFLG ($B1) is set. Full count
register access should take place in one clock cycle. A separate read/write for high byte and low byte will
give a different result than accessing them as a word.
13.4.14 16-Bit Modulus Down-Counter Control Register
Read: Anytime
Write: Anytime
MCZI — Modulus Counter Underflow Interrupt Enable Bit
MODMC — Modulus Mode Enable Bit
RDMCL — Read Modulus Down-Counter Load Bit
ICLAT — Input Capture Force Latch Action Bit
FLMC — Force Load Register into the Modulus Counter Count Register Bit
Freescale Semiconductor
When input capture latch mode is enabled (LATQ and BUFEN bit in ICSYS ($AB) are set), writing 1 to
this bit immediately forces the contents of the input capture registers TC0 to TC3 and their
corresponding 8-bit pulse accumulators to be latched into the associated holding registers. The pulse
accumulators will be automatically cleared when the latch action occurs.
Writing 0 to this bit has no effect. Read of this bit aways will return 0.
This bit is active only when the modulus down-counter is enabled (MCEN = 1). Writing a 1 into this bit
loads the load register into the modulus counter count register. This also resets the modulus counter
prescaler. Writing 0 to this bit has no effect.
When MODMC = 0, the counter starts counting and stops at $0000. Reads of this bit will return
always 0.
0 = Modulus counter interrupt is disabled.
1 = Modulus counter interrupt is enabled.
0 = The counter counts once from the value written to it and will stop at $0000.
1 = Modulus mode is enabled. When the counter reaches $0000, the counter is loaded with the
0 = Reads of the modulus count register will return the present value of the count register.
1 = Reads of the modulus count register will return the contents of the load register.
latest value written to the modulus count register.
Figure 13-35. 16-Bit Modulus Down-Counter Control Register (MCCTL)
Address: $00A6
For proper operation, the MCEN bit should be cleared before modifying the
MODMC bit to reset the modulus counter to $FF.
Reset:
Read:
Write:
MCZI
Bit 7
0
MODMC
6
0
M68HC12B Family Data Sheet, Rev. 9.1
RDMCL
5
0
NOTE
ICLAT
4
0
FLMC
3
0
MCEN
2
0
MCPR1
1
0
MCPR0
Bit 0
0
Timer Registers
179
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