MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 103

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

8.4 Operation
The FLASH EEPROM can contain program and data. On reset, it can operate as a bootstrap memory to
provide the CPU with internal initialization information during the reset sequence.
8.4.1 Bootstrap Operation Single-Chip Mode
After reset, the CPU controlling the system will begin booting up by fetching the first program address from
address $FFFE.
8.4.2 Normal Operation
The FLASH EEPROM allows a byte or aligned word read/write in one bus cycle. Misaligned word
read/write require an additional bus cycle. The FLASH EEPROM array responds to read operations only.
Write operations are ignored.
8.4.3 Program/Erase Operation
An unprogrammed FLASH EEPROM bit has a logic state of 1. A bit must be programmed to change its
state from 1 to 0. Erasing a bit returns it to a logic 1. The FLASH EEPROM has a minimum program/erase
life of 100 cycles. Programming or erasing the FLASH EEPROM is accomplished by a series of control
register writes and a write to a set of programming latches.
Programming is restricted to a single byte or aligned word at a time determined by internal signals SZ8
and ADDR0. The FLASH EEPROM must first be completely erased prior to programming final data
values. It is possible to program a location in the FLASH EEPROM without erasing the entire array, if the
new value does not require the changing of bit values from 0 to 1.
8.4.3.1 Read/Write Accesses During Program/Erase
During program or erase operations, read and write accesses may be different from those during normal
operation and are affected by the state of the control bits in the FLASH EEPROM control register
(FEECTL). The next write to any valid address to the array after LAT is set will cause the address and
data to be latched into the programming latches. Once the address and data are latched, write accesses
to the array will be ignored while LAT is set. Writes to the control registers will occur normally.
Freescale Semiconductor
FLASH EEPROM module control registers may be read or written while ENPE is asserted. If ENPE is
asserted and LAT is negated on the same write access, no programming or erasure will be performed.
ENPE
0
0
0
1
Table 8-1. Effects of ENPE, LAT, and ERAS on Array Reads
LAT
—
0
1
1
M68HC12B Family Data Sheet, Rev. 9.1
ERAS
—
—
0
1
Normal read of location addressed
Read of location being programmed
Normal read of location addressed
Read cycle is ignored
Result of Read
Operation
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