MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 254

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

16.7.3 msCAN12 Power-Down Mode
The msCAN12 is in power-down mode when either of these occurs:
When entering power-down mode, the msCAN12 immediately stops all on-going transmissions and
receptions, potentially causing CAN protocol violations.
To protect the CAN bus system from fatal consequences of violations to this rule, the msCAN12 will drive
the TxCAN pin into recessive state.
In power-down mode, no registers can be accessed.
16.7.4 Programmable Wakeup Function
The msCAN12 can be programmed to apply a low-pass filter function to the RxCAN input line while in
sleep mode. See control bit WUPM in the module control register,
Register
CAN bus lines. Such glitches can result from electromagnetic interference within noisy environments.
16.8 Timer Link
The msCAN12 generates a timer signal whenever a valid frame has been received. Because the CAN
specification defines a frame to be valid if no errors occurred before the EOF field has been transmitted
successfully, the timer signal is generated right after the EOF. A pulse of one bit time is generated. As the
msCAN12 receiver engine also receives the frames being sent by itself, a timer signal also is generated
after a successful transmission.
The previously described timer signal can be routed into the on-chip timer interface module (TIM). This
signal is connected to the timer n channel m input
bit in the CMCR0.
After timer n has been programmed to capture rising edge events, it can be used under software control
to generate 16 bit-time stamps which can be stored with the received message.
16.9 Clock System
Figure 16-7
scheme the msCAN12 is able to handle CAN bus rates ranging from 10 kbps to 1 Mbps.
1. The timer channel being used for the timer link is integration dependent.
254
msCAN12 Controller
•
•
CPU is in stop mode.
CPU is in wait mode and the CSWAI bit is set. See
0
and
1. This feature can be used to protect the msCAN12 from wakeup due to short glitches on the
shows the structure of the msCAN12 clock generation circuitry. With this flexible clocking
16.12.2 msCAN12 Module Control Register
The user should be careful that the msCAN12 is not active when
power-down mode is entered. The recommended procedure is to put the
msCAN12 into sleep mode before the STOP instruction — or the WAI
instruction, if CSWAI is set — is executed.
M68HC12B Family Data Sheet, Rev. 9.1
NOTE
(1)
under the control of the timer link enable (TLNKEN)
16.12.1 msCAN12 Module Control Register
1.
16.12.2 msCAN12 Module Control
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