MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 135

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

11.2.11 PWM Channel Duty Registers 0–3
Read: Anytime
Write: Anytime
The value in each duty register determines the duty of the associated PWM channel. When the duty value
is equal to the counter value, the output changes state. If the register is written while the channel is
enabled, the new value is held in a buffer until the counter rolls over or the channel is disabled. Reading
this register returns the most recent value written.
If the duty register is greater than or equal to the value in the period register, there is no duty change in
state. If the duty register is set to $FF, the output is always in the state which would normally be the state
opposite the PPOLx value.
Left-aligned output mode (CENTR = 0):
Center-aligned output mode (CENTR = 1):
Freescale Semiconductor
Duty cycle = [(PWDTYx + 1) / (PWPERx + 1)] × 100%(PPOLx = 1)
Duty cycle = [(PWPERx − PWDTYx) / (PWPERx + 1)] × 100%(PPOLx = 0)
Duty cycle = [(PWPERx − PWDTYx) / PWPERx] × 100%(PPOLx = 0)
Duty cycle = (PWDTYx / PWPERx) × 100%(PPOLx = 1)
Address: $0050
Address: $0051
Address: $0052
Address: $0053
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Figure 11-20. PWM Channel Duty Register 0 (PWDTY0)
Figure 11-21. PWM Channel Duty Register 1 (PWDTY1)
Figure 11-22. PWM Channel Duty Register 2 (PWDTY2)
Figure 11-23. PWM Channel Duty Register 3 (PWDTY3)
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
1
1
1
1
Bit 6
Bit 6
Bit 6
Bit 6
6
1
6
1
6
1
6
1
M68HC12B Family Data Sheet, Rev. 9.1
Bit 5
Bit 5
Bit 5
Bit 5
5
1
5
1
5
1
5
1
Bit 4
Bit 4
Bit 4
Bit 4
4
1
4
1
4
1
4
1
Bit 3
Bit 3
Bit 3
Bit 3
3
1
3
1
3
1
3
1
Bit 2
Bit 2
Bit 2
Bit 2
2
1
2
1
2
1
2
1
Bit 1
Bit 1
Bit 1
Bit 1
1
1
1
1
1
1
1
1
PWM Register Descriptions
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
1
1
1
1
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