MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 61

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

3.3.3 Index Registers X and Y
Index registers X and Y are used for indexed addressing. Indexed addressing adds the value in an index
register to a constant or to the value in an accumulator to form the effective address of the operand.
Index registers X and Y can also serve as temporary data storage locations.
3.3.4 Stack Pointer
The stack pointer (SP) contains the last stack address used. The CPU12 supports an automatic program
stack that is used to save system context during subroutine calls and interrupts.
The stack pointer can also serve as a temporary data storage location or as an index register for indexed
addressing.
Freescale Semiconductor
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 15
Bit 15
Bit 15
SP15
X15
Y15
SP14
X14
Y14
14
14
14
The LDX and STX instructions can be used to manipulate data in and out
of index register X.
The LDY and STY instructions can be used to manipulate data in and out
of index register Y.
The LDS and STS instructions can be used to manipulate data in and out
of the stack pointer.
SP13
X13
Y13
13
13
13
SP12
X12
Y12
12
12
12
SP11
X11
Y11
11
11
11
Figure 3-5. Index Register X (X)
Figure 3-6. Index Register Y (Y)
M68HC12B Family Data Sheet, Rev. 9.1
Figure 3-7. Stack Pointer (SP)
SP10
X10
Y10
10
10
10
SP9
X9
Y9
9
9
9
Unaffected by reset
Unaffected by reset
Unaffected by reset
NOTE
NOTE
NOTE
SP8
X8
Y8
8
8
8
SP7
X7
Y7
7
7
7
SP6
X6
Y6
6
6
6
SP5
X5
Y5
5
5
5
SP4
X4
Y4
4
4
4
SP3
X3
Y3
3
3
3
SP2
X2
Y2
2
2
2
CPU Registers
SP1
X1
Y1
1
1
1
Bit 0
Bit 0
Bit 0
SP0
X0
Y0
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