MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 130

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Pulse-Width Modulator (PWM)
11.2.3 PWM Enable Register
Read: Anytime
Write: Anytime
Setting any of the PWENx bits causes the associated port P line to become an output regardless of the
state of the associated data direction register (DDRP) bit. This does not change the state of the data
direction bit. When PWENx returns to 0, the data direction bit controls I/O direction. On the front end of
the PWM channel, the scaler clock is enabled to the PWM circuit by the PWENx enable bit being high.
When all four PWM channels are disabled, the prescaler counter shuts off to save power. There is an
edge-synchronizing gate circuit to guarantee that the clock is only enabled or disabled at an edge.
PWEN3 — PWM Channel 3 Enable Bit
PWEN2 — PWM Channel 2 Enable Bit
PWEN1 — PWM Channel 1 Enable Bit
PWEN0 — PWM Channel 0 Enable Bit
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The pulse modulated signal will be available at port P bit 3 when its clock source begins its next cycle.
The pulse modulated signal will be available at port P bit 2 when its clock source begins its next cycle.
The pulse modulated signal will be available at port P bit 1 when its clock source begins its next cycle.
The pulse modulated signal will be available at port P bit 0 when its clock source begins its next cycle.
0 = Channel 3 disabled
1 = Channel 3 enabled
0 = Channel 2 disabled
1 = Channel 2 enabled
0 = Channel 1 disabled
1 = Channel 1 enabled
0 = Channel 0 disabled
1 = Channel 0 enabled
Address: $0042
Reset:
Read:
Write:
Bit 7
0
0
Figure 11-6. PWM Enable Register (PWEN)
= Unimplemented
6
0
0
M68HC12B Family Data Sheet, Rev. 9.1
5
0
0
4
0
0
PWEN3
3
0
PWEN2
2
0
PWEN1
1
0
Freescale Semiconductor
PWEN0
Bit 0
0