DS3141+ Maxim Integrated Products, DS3141+ Datasheet - Page 64

• Manufacturer Part Number: DS3141+
• Description: IC FRAMER DS3/E3 SNGL 144CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3141+

• Controller Type: DS3/E3 Framer
• Interface: LIU
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 80mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit #
Name
Default
Note: See
Bit 0: Transmit FEAC Idle Latched (TFIL). This latched status bit is set to 1 when the TFI status bit in the
register goes high. TFIL is cleared when the host processor writes a 1 to it and is not set again until TFI goes high
again. When TFIL is set, it can cause a hardware interrupt to occur if the TFIIE bit in the
FEACIE bit in the
interrupt-enable bits are cleared. This bit can be used to determine when the FEAC codeword transmission has
finished, and thus a new codeword can be transmitted.
Bit 1: Receive FEAC Codeword Detected Latched (RFCDL). This latched status bit is set to 1 when the RFCD
status bit in the
again until RFCD goes high again. When RFCDL is set, it can cause a hardware interrupt to occur if the RFCDIE
bit in the
bit is cleared or one or both of the interrupt-enable bits are cleared.
Bit 2: Receive FEAC Idle Latched (RFIL). This latched status bit is set to 1 when the RFI status bit in the
register goes high. RFIL is cleared when the host processor writes a 1 to it and is not set again until RFI goes high
again. When RFIL is set, it can cause a hardware interrupt to occur if the RFIIE bit in the
FEACIE bit in the
interrupt-enable bits are cleared. This bit can be used to determine when the FEAC receiver has stopped receiving
codewords, which can mark the end of an alarm situation.
Bit 3: Receive FEAC FIFO Not-Empty Latched (RFFNL). This latched status bit is set to 1 when the RFFE bit in
the
RFFE bit goes low again. When RFFNL is set, it can cause a hardware interrupt to occur if the RFFNIE bit in the
FSRIE
cleared or one or both of the interrupt-enable bits are cleared. This bit can be used to determine when to read
FEAC codeword(s) from the FIFO.
Bit 4: Receive FEAC FIFO Overflow Latched (RFFOL). This latched status bit is set to 1 when the receive FEAC
controller has attempted to write to an already full receive FEAC FIFO and the current incoming FEAC codeword is
lost. RFFOL is cleared when the host processor writes a 1 to it and is not set again until another FIFO overflow
occurs (i.e., the receive FEAC FIFO has been read and then fills beyond capacity). When RFFOL is set, it can
cause a hardware interrupt to occur if the RFFOIE bit in the
register are both set. The interrupt is cleared when this bit is cleared or one or both of the interrupt-enable bits are
cleared.
Register Name:
Register Description:
Register Address:
FSR
register and the FEACIE bit in the
Figure 7-8
register goes low. RFFNL is cleared when the host processor writes a 1 to it and is not set again until the
FSRIE
FSR
N/A
register and the FEACIE bit in the
—
7
for details on the interrupt logic for the status bits in the BSRL register.
MSRIE
MSRIE
register goes high. RFCDL is cleared when the host processor writes a one to it and is not set
register are both set. The interrupt is cleared when this bit is cleared or one or both of the
register are both set. The interrupt is cleared when this bit is cleared or one or both of the
N/A
—
6
FSRL
FEAC Status Register Latched
62h
N/A
—
5
MSRIE
MSRIE
register are both set. The interrupt is cleared when this bit is
RFFOL
64 of 88
—
4
register are both set. The interrupt is cleared when this
FSRIE
RFFNL
—
3
register and the FEACIE bit in the
RFIL
—
2
FSRIE
RFCDL
FSRIE
—
1
register and the
register and the
TFIL
—
0
MSRIE
FSR
FSR