DS3141+ Maxim Integrated Products, DS3141+ Datasheet - Page 47

• Manufacturer Part Number: DS3141+
• Description: IC FRAMER DS3/E3 SNGL 144CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3141+

• Controller Type: DS3/E3 Framer
• Interface: LIU
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 80mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 3: Repetitive Pattern Length (RPL[3:0]). RPL3 is the MSB and RPL0 is the LSB of a nibble that
describes how long the repetitive pattern is. The valid range is 17 (0000) to 32 (1111). These bits are ignored if the
BERT is programmed for a pseudorandom pattern or an alternating word pattern. To create repetitive patterns
fewer than 17 bits in length, the user must set the length to an integer multiple of the desired length that is less
than or equal to 32. For example, to create a 6-bit pattern, set the length to 18 (0001), 24 (0111), or 30 (1101).
Bits 4 to 6: Pattern Select (PS[2:0]). This field specifies the type of pattern to be generated. After configuring
these bits, the TC bit in the
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: Single Bit-Error Insert (SBE). A low-to-high transition creates a single bit error. Must be cleared and set
again for a subsequent bit error to be inserted.
Bits 1 to 3: Error Insert Bits (EIB[2:0]). Automatically insert bit errors at the prescribed rate into the generated
data pattern. Useful for verifying error detection operation.
Length
17 bits
21 bits
25 bits
29 bits
PS[2:0]
EIB[2:0]
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
Code
0000
0100
1000
1100
No errors automatically inserted
10
10
10
10
10
10
10
N/A
N/A
Alternating Word Pattern
—
—
7
7
–1
–2
–3
–4
–5
–6
–7
Repetitive Pattern
(1 error per 10 bits)
(1 error per 100 bits)
(1 error per 1000 bits)
(1 error per 10,000 bits)
(1 error per 100,000 bits)
(1 error per 1,000,000 bits)
(1 error per 10,000,000 bits)
2
PATTERN
20
Invalid
Invalid
2
- 1 QRSS
2
2
ERROR RATE INSERTED
15
23
31
BCR1
- 1
- 1
- 1
PS2
N/A
Length
18 bits
22 bits
26 bits
30 bits
—
6
0
6
BCR3
BERT Control Register 3
32h
register must be toggled to reconfigure the pattern generator.
BCR2
BERT Control Register 2
31h
PS1
Code
0001
0101
1001
1101
N/A
—
5
0
5
14, 15
17, 20
18, 23
28, 31
TAPS
—
—
—
—
47 of 88
PS0
N/A
—
0
4
4
Length
19 bits
23 bits
27 bits
31 bits
ITU O.151 (for DS3)
ITU O.151 (for E3)
SPECIFICATION
RPL3
EIB2
3
0
3
0
T1.403
(none)
Code
0010
0110
1010
1110
—
—
—
—
RPL2
EIB1
2
0
2
0
Length
20 bits
24 bits
28 bits
32 bits
TINV
RPL1
—
—
—
—
EIB0
1
0
1
0
1
0
1
0
Code
0011
0111
1011
1111
RPL0
RINV
SBE
—
—
—
—
1
0
1
0
0
0
0
0