DS3141+ Maxim Integrated Products, DS3141+ Datasheet - Page 22

• Manufacturer Part Number: DS3141+
• Description: IC FRAMER DS3/E3 SNGL 144CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3141+

• Controller Type: DS3/E3 Framer
• Interface: LIU
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 80mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.6 Common and Line Interface Registers
This section describes the registers responsible for top-level configuration, control, and status of each framer,
including resets, clocks, pin controls, and line interface functions.
Table 7-C. Common Line Interface Register Map
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
This register is a global resource and is mapped into address 00h in every framer in the device.
Bits 0 to 7: Device ID (ID[7:0]). Read-only. Contact the factory for details on the meaning of the ID bits.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: Framer Reset (RST). When this bit is set to logic 1, it forces all the internal registers in the framer (except
this RST bit) to their default state. Only the framer associated with this register is reset. RST must be high for a
minimum of 100ns and then returned low. This register bit is logically ORed with the RST pin.
Bit 1: Framer Disable (DISABLE). Setting this bit disables the framer by stopping all clocks. This reduces the
power the framer requires. After the framer is enabled again by clearing this bit, the RST bit must be toggled to
initialize the framer again. Toggling the RST bit when DISABLE = 1 automatically enables the framer again.
Bit 2: Transmit Unframed All Ones (TUA1). Enables the transmission of an unframed all-ones pattern on
TPOS/TNEG or TNRZ. This pattern is sometimes called physical AIS.
ADDR
0Ah
00h
01h
02h
03h
04h
05h
06h
08h
09h
0 = normal operation
1 = force all internal registers to their default values
0 = enable framer
1 = disable framer
0 = disable transmission of unframed all ones
1 = enable transmission of unframed all ones (reset default value)
REGISTER
LOTCMC
MSRIE
MSRL
ISR1
MSR
MC1
MC2
MC3
MC4
MC5
ID7
ID
—
7
7
0
TDENMS
RDENMS
LOTCMC
LORCIE
OSTCS
LORCL
RNEGI
LORC
BIT 7
N/A
ID6
ZCSD
ID7
—
6
6
0
ID
ID Register
00h
MC1
Master Configuration Register 1
01h
LOTCIE
TCCLK
TSOFC
ROOFI
RPOSI
LOTCL
ZCSD
LOTC
BIT 6
ID6
N/A
ID5
—
BIN
5
0
5
TOHENI
T3E3IE
RLOSI
RCLKI
BIT 5
T3E3
BIN
N/A
N/A
N/A
ID5
MECU
22 of 88
ID4
—
4
4
0
TNEGH
FEACIE
RDATH
MECU
FEAC
BIT 4
TOHI
N/A
N/A
N/A
ID4
AECU
ID3
—
3
3
0
HDLCIE
TPOSH
RSOFI
TSOFI
AECU
HDLC
BIT 3
INT4
N/A
N/A
ID3
TUA1
2
1
ID2
—
2
ROCLKI
BERTIE
TICLKI
TNEGI
BERT
BIT 2
TUA1
INT3
DLB
N/A
ID2
DISABLE
1
0
ID1
—
DISABLE
COVFIE
1
COVFL
RDATI
TPOSI
TDATI
COVF
BIT 1
INT2
LLB
ID1
RST
ID0
—
RDENI
0
0
TDENI
OSTIE
TCLKI
0
OSTL
BIT 0
INT1
RST
PLB
N/A
ID0