DS3141+ Maxim Integrated Products, DS3141+ Datasheet - Page 53

• Manufacturer Part Number: DS3141+
• Description: IC FRAMER DS3/E3 SNGL 144CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3141+

• Controller Type: DS3/E3 Framer
• Interface: LIU
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 80mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 23: BERT Bit-Error Counter (BEC[23:0]). The BBECR registers are loaded with the value of the internal
BERT error counter when the LC control bit in the
received data bit that does not match the expected pattern. The error counter starts counting when the BERT goes
into receive synchronization (SYNC = 1) and continues counting even if the BERT loses sync. The error counter
saturates and does not roll over. Upon saturation, the BECO status bit in the
toggled, the error count is loaded into the BBECR registers and the internal error counter is cleared. If the BERT is
in sync when LC is toggled, the error counter continues to count up from zero. If the BERT is out of sync when LC
is toggled, the error counter is held at zero until the BERT regains sync. The host processor should toggle LC after
the BERT has synchronized and then toggle LC again when the error-checking period is complete. If the framer
loses synchronization during this period, then the counting results are suspect.
7.10 HDLC Controller
Each framer contains an on-board HDLC controller with 256-byte buffers in the transmit and receive paths. When
the framer is operated in the DS3 C-Bit Parity mode, the HDLC transmitter and receiver are connected to the three
C-bits in M-subframe 5. When the framer is operated in the E3 mode, the user has the option to connect the HDLC
transmitter to the Sn bit, while the HDLC receiver is always connected to the Sn bit in the receive data. If the host
processor does not wish to use the HDLC controller for the Sn bit, then the status provided by the HDLC controller
should be ignored. On the transmit side, the host processor selects the source of the Sn bit through the E3SnC0
and E3SnC1 controls bits in the
7.10.1 Receive Operation
On reset, the receive HDLC controller flushes the receive FIFO and begins searching for a new incoming HDLC
packet. It then performs a bit-by-bit search for an HDLC packet and when one is detected, it zero destuffs the
incoming data stream, automatically byte aligns to it, and places the incoming bytes into the receive FIFO as they
are received. The first byte of each packet is marked in the receive FIFO by setting the opening byte (OBYTE) bit.
Upon detecting a closing flag, the receive HDLC controller checks the 16-bit CRC to see if the packet is valid or not
and then marks the last byte of the packet in the receive FIFO by setting the closing byte (CBYTE) bit. The CRC is
not passed to the receive FIFO. When the CBYTE bit is set, the host processor can obtain the status of the
incoming packet through the packet status bits (PS0 and PS1). Incoming packets can be separated by as few as
one flag or by two flags that share a common zero. If the receive FIFO ever fills beyond capacity, the rest of the
incoming packet data is discarded, and the receive FIFO overrun (ROVRL) status bit is set. If such a scenario
occurs, then the last packet in the FIFO is suspect and should be discarded. When an overflow occurs, the receive
BEC15
BEC23
BEC7
7
0
7
0
7
0
BEC14
BEC22
BEC6
6
0
6
0
6
0
T3E3CR1
BBECR1
BERT Bit-Error Counter Register 1 (lower byte)
44h
BBECR2
BERT Bit Error Counter Register 2
45h
BBECR3
BERT Bit Error Counter Register 3 (upper byte)
46h
BEC13
BEC21
BEC5
register. The HDLC controller is not used in the DS3 M23 mode.
5
0
5
0
5
0
BCR1
BEC12
BEC20
53 of 88
BEC4
0
0
0
4
4
4
register is toggled. This 24-bit counter increments for each
BEC11
BEC19
BEC3
3
0
3
0
3
0
BSR
BEC10
BEC18
BEC2
2
0
2
0
2
0
register is set. When the LC bit is
BEC17
BEC1
BEC9
1
0
1
0
1
0
BEC16
BEC0
BEC8
0
0
0
0
0
0