DS3141+ Maxim Integrated Products, DS3141+ Datasheet - Page 19

• Manufacturer Part Number: DS3141+
• Description: IC FRAMER DS3/E3 SNGL 144CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3141+

• Controller Type: DS3/E3 Framer
• Interface: LIU
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 80mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 7-2. Transmit Clock Block Diagram
7.2.2 Loss-of-Clock Detection
The LOTC and LORC (loss-of-receive clock) status bits in the
receive (RCLK) clocks are stopped, respectively. The clocks are monitored with the system clock (SCLK), which
must be running for the loss-of-clock circuits to function properly. The LOTC and LORC status bits are set when
TICLK or RCLK have been stopped high or low for between 9 and 21 clock periods (depending on SCLK
frequency). The LOTC and LORC status bits are cleared after the device detects a few edges of the monitored
clock.
7.3 Receiver Logic
In the normal operating mode, the signals on RPOS and RNEG are decoded as an HDB3 signal in E3 mode or as
a B3ZS signal in DS3 mode and output on the RDAT pin. The input signal is monitored for loss-of-signal, bipolar
violations, excessive zeroes, AIS, and unframed all ones, and after decoding, is sent to the BERT and
synchronizer. When the synchronizer finds the framing pattern in the overhead bits, it clears the out-of-frame
indication (ROOF) and aligns the start-of-frame (RSOF) and data-enable (RDEN) signals to the signal on RDAT. If
the framing pattern is lost, then ROOF is set and the framing pattern is searched for again. While the framing
pattern is being searched for, the RSOF and RDEN signals maintain the alignment with the last known position of
the framing pattern. If a framing pattern is found in a new position, the RSOF and RDEN signals align with the new
pattern position and the COFAL status bit is set in the
are generated, but have no relationship with any framing pattern until one is found. The signal on the ROOF pin
can be monitored using the OOF bit in the
the DLB bit in the
the framer and synchronizer logic to be checked in order to isolate a problem in the system. The BERT can monitor
either the payload or the entire signal for expected test patterns.
Figure 7-3. Receiver Block Diagram
FROM Tx DLB
TICLK
RCLK
RNEG
RPOS
RCLK
LOTCMC
MC2
DLB
LOTC
register, RCLK, RPOS, and RNEG are replaced with TICLK, TPOS, and TNEG. This allows
LORC
PLB
DLB
DECODER
B3ZS
HDB
AMI
T3E3SR
1
0
register. When the diagnostic loopback mode is enabled using
19 of 88
T3E3SRL
TDAT
INTERNAL TCLK
SYNCHRONIZER
MSR
LLB
E3 G.751
1
0
register. After reset, the RSOF and RDEN signals
DS3
Rx BERT
register are set when the transmit (TICLK) and
FROM Tx BERT
TCLK
TO PLB MUX
RLOS
ROOF
RSOF
RDEN
RDAT
ROCLK