DS3141+ Maxim Integrated Products, DS3141+ Datasheet - Page 28

• Manufacturer Part Number: DS3141+
• Description: IC FRAMER DS3/E3 SNGL 144CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3141+

• Controller Type: DS3/E3 Framer
• Interface: LIU
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 80mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.6.1 Master Status Register (MSR)
The master status register (MSR) is a special status register that helps the host processor quickly locate changes
in device status. Each major block in the framer has a status bit in the MSR. When an alarm or event occurs in one
of these blocks, the device can be configured to set the appropriate bit in the MSR. The latched status bits in the
MSRL
strategies, the host processor should read the
read the
service.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 1: Counter Overflow Event (COVF). This real-time status bit is set to 1 if any of the error counters saturate
(the error counters saturate when full). This bit is cleared when the error counters are cleared. The error counters
are discussed in Section 7.8.
Bit 2: Change in BERT Status (BERT). This real-time status bit is set when any of the bits in the
are set and the corresponding bits in the
latched status bits in the
The setting of this status bit can cause a hardware interrupt to occur if the BERTIE bit in the
to 1. The interrupt is cleared when this bit is cleared or the interrupt-enable bit in the
Bit 3: Change in HDLC Status (HDLC). This real-time status bit is set when any of the bits in the
are set and the corresponding bits in the
latched status bits in the
The setting of this status bit can cause a hardware interrupt to occur if the HDLCIE bit in the
to 1. The interrupt is cleared when this bit is cleared or the interrupt-enable bit in the
Bit 4: Change in FEAC Status (FEAC). This real-time status bit is set when any of the bits in the
are set and the corresponding bits in the
latched status bits in the
The setting of this status bit can cause a hardware interrupt to occur if the FEACIE bit in the
to 1. The interrupt is cleared when this bit is cleared or the interrupt-enable bit in the
Bit 5: Change in DS3/E3 Framer Status (T3E3). This real-time status bit is set when any of the bits in the
T3E3SRL
cleared when the latched status bits in the
T3E3SRIE
bit in the
MSRIE
Bit 6: Loss-of-Transmit Clock Detected (LOTC). This real-time status bit is set when the device detects that the
TICLK input pin has not toggled for between 9 and 21 clock periods. This bit is cleared when a clock is detected at
the TICLK input. The system clock (SCLK) is used to check for the presence of the TICLK. On reset the LOTC
status bit is set for a few clock cycles and then cleared if TICLK is present.
Bit 7: Loss-of-Receive Clock Detected (LORC). This real-time status bit is set when the device detects that the
RCLK input pin has not toggled for between 9 and 21 clock periods. This bit is cleared when a clock is detected at
the RCLK input. The system clock (SCLK) checks for the presence of the RCLK. On reset the LORC status bit is
set for a few clock cycles and then cleared if RCLK is present.
can also cause a hardware interrupt to occur. In both interrupt-based and polling-based device servicing
register is cleared.
MSRIE
MSRL
register are set and the corresponding bits in the
register are cleared. The setting of this status bit can cause a hardware interrupt to occur if the T3E3IE
LORC
—
register is set to 1. The interrupt is cleared when this bit is cleared or the interrupt-enable bit in the
register of each framer that needs service to determine which blocks within the framer need
7
BSRL
HSRL
FSRL
LOTC
—
6
register are cleared or the interrupt-enable bits in the
register are cleared or the interrupt-enable bits in the
register are cleared or the interrupt-enable bits in the
MSR
Master Status Register
08h
T3E3
—
5
BSRIE
HSRIE
FSRIE
T3E3SRL
ISR1
interrupt-enable register are set. This bit is cleared when the
interrupt-enable register are set. This bit is cleared when the
interrupt-enable register are set. This bit is cleared when the
28 of 88
FEAC
register to determine which framers need service and then
—
4
register are cleared or the interrupt-enable bits in the
T3E3SRIE
HDLC
—
3
interrupt-enable register are set. This bit is
BERT
—
2
MSRIE
MSRIE
MSRIE
HSRIE
BSRIE
FSRIE
register is cleared.
register is cleared.
register is cleared.
COVF
MSRIE
MSRIE
MSRIE
—
register are cleared.
register are cleared.
register are cleared.
1
HSRL
BSRL
FSRL
register is set
register is set
register is set
N/A
—
register
register
register
0