DS3141+ Maxim Integrated Products, DS3141+ Datasheet - Page 4

• Manufacturer Part Number: DS3141+
• Description: IC FRAMER DS3/E3 SNGL 144CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3141+

• Controller Type: DS3/E3 Framer
• Interface: LIU
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 80mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers
LIST OF FIGURES
Figure 1-1. Block Diagram ....................................................................................................................... 6
Figure 2-1. Application Example: 12-Port Unchannelized DS3/E3 Card .................................................. 6
Figure 5-1. Transmit Formatter Timing .................................................................................................. 11
Figure 5-2. Receive Framer Timing ....................................................................................................... 13
Figure 6-1. Status Register Interrupt Flow ............................................................................................. 17
Figure 7-1. Transmit Data Block Diagram.............................................................................................. 18
Figure 7-2. Transmit Clock Block Diagram ............................................................................................ 19
Figure 7-3. Receiver Block Diagram ...................................................................................................... 19
Figure 7-4. MSR Status Bit Interrupt Signal Flow................................................................................... 31
Figure 7-5. T3E3SR Status Bit Interrupt Signal Flow ............................................................................. 39
Figure 7-6. BERT Status Bit Interrupt Signal Flow ................................................................................. 50
Figure 7-7. HDLC Status Bit Interrupt Signal Flow................................................................................. 59
Figure 7-8. FEAC Status Bit Interrupt Signal Flow ................................................................................. 65
Figure 9-1. JTAG Block Diagram ........................................................................................................... 69
Figure 9-2. JTAG TAP Controller State Machine ................................................................................... 70
Figure 11-1. Data Path Timing Diagram ................................................................................................ 75
Figure 11-2. Line Loopback Timing Diagram ......................................................................................... 75
Figure 11-3. SCLK Clock Timing ........................................................................................................... 76
Figure 11-4. Microprocessor Interface Timing Diagram (Nonmultiplexed).............................................. 77
Figure 11-5. Microprocessor Interface Timing Diagram (Multiplexed) .................................................... 79
Figure 11-6. JTAG Interface Timing Diagram ........................................................................................ 81
Figure 12-1. DS3141 Pin Configuration ................................................................................................. 83
Figure 12-2. DS3142 Pin Configuration ................................................................................................. 84
Figure 12-3. DS3143 Pin Configuration ................................................................................................. 85
Figure 12-4. DS3144 Pin Configuration ................................................................................................. 86
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