DS3141+ Maxim Integrated Products, DS3141+ Datasheet - Page 26

• Manufacturer Part Number: DS3141+
• Description: IC FRAMER DS3/E3 SNGL 144CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3141+

• Controller Type: DS3/E3 Framer
• Interface: LIU
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 80mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: RDEN Invert Enable (RDENI)
Bit 1: RDAT Invert Enable (RDATI)
Bit 2: ROCLK Invert Enable (ROCLKI)
Bit 3: RSOF Invert Enable (RSOFI)
Bit 4: RDAT Force High (RDATH). This bit is set to logic 1 at reset, which puts an all-ones signal on the RDAT
pin. This pin should be cleared once the device has framed to a valid signal. The RDAT pin can be forced low by
setting both the RDATH and RDATI control bits.
Bit 5: RLOS Invert Enable (RLOSI)
Bit 6: ROOF Invert Enable (ROOFI)
Bit 7: Receive Data-Enable Mode Select (RDENMS). When this bit is logic 0, the RDEN/RGCLK output has the
RDEN (data enable) function. RDEN asserts during payload bit times and de-asserts during overhead bit times.
When this bit is logic 1, RDEN/RGCLK has the RGCLK (gapped clock) function. RGCLK pulses during payload bit
times and is suppressed during overhead bit times. See
0 = do not invert the RDEN signal (normal mode)
1 = invert the RDEN signal (inverted mode)
0 = do not invert the RDAT signal (normal mode)
1 = invert the RDAT signal (inverted mode)
0 = do not invert the ROCLK signal (normal mode)
1 = invert the ROCLK signal (inverted mode)
0 = do not invert the RSOF signal (normal mode)
1 = invert the RSOF signal (inverted mode)
0 = do not force RDAT high (normal mode)
1 = force RDAT high (default reset mode)
0 = do not invert the RLOS signal (normal mode)
1 = invert the RLOS signal (inverted mode)
0 = do not invert the ROOF signal (normal mode)
1 = invert the ROOF signal (inverted mode)
0 = RDEN (data enable) mode
1 = RGCLK (gapped clock) mode
RDENMS
7
0
ROOFI
6
0
MC4
Master Configuration Register 4
04h
RLOSI
5
0
RDATH
26 of 88
1
4
Figure 5-2
RSOFI
for timing information.
3
0
ROCLKI
2
0
RDATI
1
0
RDENI
0
0