DS3141+ Maxim Integrated Products, DS3141+ Datasheet - Page 63

• Manufacturer Part Number: DS3141+
• Description: IC FRAMER DS3/E3 SNGL 144CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3141+

• Controller Type: DS3/E3 Framer
• Interface: LIU
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 80mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.11.1 FEAC Register Description
Table 7-I. FEAC Register Map
Bits 0, 1: Transmit FEAC Codeword Select Bits 0 and 1 (TFS[1:0]). These two bits control which of the two
available codewords are to be generated. Both TFS0 and TFS1 are edge-triggered; a change from 00 to any other
value starts the desired FEAC transmission. Actions 01 and 10 continue to completion even if TFS is subsequently
written with 00. Action 11 transmits at least 10 codewords before being terminated by TFS = 00. To initiate a new
action, the host must select the idle state (TFS = 00) before selecting the new action.
Bit 2: Receive FEAC Reset (RFR). A 0-to-1 transition resets the FEAC receiver and flushes the receive FEAC
FIFO. This bit must be cleared before generating a subsequent reset.
Bit 0: Transmit FEAC Idle (TFI). This real-time status bit is set when the FEAC transmitter is sending the all-ones
idle code. It is cleared when the FEAC transmitter is sending a FEAC codeword.
Bit 1: Receive FEAC Codeword Detected (RFCD). This real-time status bit is set each time the FEAC receiver
has detected and validated a new FEAC codeword. It is cleared when the validated codeword is no longer present
on the FEAC channel.
Bit 2: Receive FEAC Idle (RFI). This real-time status bit is set when the FEAC controller has detected 16
consecutive 1s. It is cleared when the FEAC receiver has detected and validated a new FEAC codeword.
Bit 3: Receive FEAC FIFO Empty (RFFE). This real-time status bit is set when the receive FEAC FIFO is empty,
and thus RFF[5:0] contains no valid information. It is cleared when the receive FIFO contains one or more
codewords.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
TFS[1:0]
ADDR
60h
61h
62h
63h
64h
65h
66h
00
01
10
11
REGISTER
TFEACA
TFEACB
Idle state; do not generate a FEAC codeword (send all ones)
Send codeword A 10 times followed by all ones
Send codeword A 10 times followed codeword B 10 times followed by all ones
Send codeword A continuously (sent at least 10 times)
RFEAC
FSRIE
FSRL
N/A
N/A
FCR
FSR
—
—
7
7
BIT 7
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
—
—
6
6
FCR
FEAC Control Register
60h
FSR
FEAC Status Register
61h
BIT 6
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
—
—
5
5
ACTION
TFCA5
TFCB5
BIT 5
RFF5
N/A
N/A
N/A
N/A
63 of 88
N/A
N/A
—
—
4
4
RFFOIE
RFFOL
TFCA4
TFCB4
BIT 4
RFF4
N/A
N/A
RFFE
N/A
—
—
3
3
RFFNIE
RFFNL
TFCA3
TFCB3
RFFE
BIT 3
RFF3
N/A
RFR
RFI
—
2
0
2
TFCA2
TFCB2
RFIIE
RFF2
BIT 2
RFR
RFIL
RFI
RFCD
TFS1
—
RFCDIE
1
0
1
RFCDL
TFCA1
TFCB1
RFCD
RFF1
BIT 1
TFS1
TFS0
TFCA0
TFCB0
TFI
—
BIT 0
TFS0
TFIIE
RFF0
TFIL
0
0
0
TFI