DS3141+ Maxim Integrated Products, DS3141+ Datasheet - Page 62

• Manufacturer Part Number: DS3141+
• Description: IC FRAMER DS3/E3 SNGL 144CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3141+

• Controller Type: DS3/E3 Framer
• Interface: LIU
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 80mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note 1: The host processor should always write to THDLC1 first followed by THDLC2. Writing to THDLC2 latches the data from both THDLC1
Note 2: THDLC1 and THDLC2 are write-only registers. Data read from these registers is undefined.
Note 3: The transmit FIFO can be filled to a maximum capacity of 256 bytes. When the transmit FIFO is full, it does not latch additional data.
Bits 0 to 7: Transmit FIFO Data (D[7:0]). Data for the transmit FIFO is written to these bits. D0 is the LSB and is
transmitted first, while D7 is the MSB and is transmitted last.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: Transmit Message End (TMEND). This bit is used to delineate packets in the transmit FIFO. It should be
set to 1 when the last byte of a message is written to the THDLC1 register. When set to 1, TMEND indicates that
the message is complete and that the HDLC controller should calculate and append the CRC checksum (FCS) and
at least two flags (7Eh). This bit should be set to 0 for all other data written to the FIFO. All outgoing HDLC
messages must be at least two bytes long.
7.11 FEAC Controller
The DS3 C-Bit Parity far-end alarm and control (FEAC) channel carries repeating 16-bit codewords of the form
0xxxxxx011111111 (rightmost bit transmitted first), where x can be 0 or 1. These codewords are used to send
alarm or status information from the far end to the near end, and send loopback commands to the far end.
Each DS314x framer contains an on-board FEAC controller. When the framer is in DS3 C-Bit Parity mode, the
FEAC controller sources and sinks the FEAC channel (the third C-bit in M-subframe 1). When the framer is in E3
mode, the FEAC receiver is always connected to the E3 national bit (Sn, bit 12 of the E3 frame). If the host
processor does not wish to use the FEAC controller for processing the E3 national bit, then it should ignore the
status provided by the FEAC receiver. The FEAC transmitter can be provisioned to source the E3 national bit by
setting T3E3CR1:E3SnC[1:0] = 10. The FEAC controller is not used in DS3 M23 framing mode.
The FEAC transmitter can be configured to transmit one codeword 10 times, one codeword continuously, or one
codeword 10 times followed by another codeword 10 times. This last option is useful for sending loopback
commands where the loopback activate/deactivate command must be followed by the code for line to be looped
back. FEAC codewords are transmitted at least 10 times. When the FEAC transmitter is not sending codewords, it
enters the idle state where it transmits all ones on the FEAC channel and sets the transmit FEAC idle bit (FSR:TFI)
to 1.
The FEAC receiver does a bit-by-bit search for a data pattern matching the form of a FEAC codeword. When a
codeword is found, the receiver validates the codeword by checking to see that the same codeword is found in
three consecutive opportunities. After a codeword is validated, the receiver sets the receive FEAC codeword-detect
status bit (FSR:RFCD) and writes the codeword into the receive FEAC FIFO for the host processor to read. The
host processor can use the RFCD or receive FEAC FIFO empty (RFFE) status bits to know when to read the
receive FEAC FIFO. The receive FEAC FIFO is four codewords deep. If the FIFO is full when the FEAC receiver
attempts to write a new codeword, the new codeword is discarded and the receive FEAC FIFO Overflow status bit
(RFFOL) is set. The FEAC receiver clears the RFCD status bit when the valid codeword is no longer present on the
FEAC channel (i.e., when a different codeword is received twice in a row).
and THDLC2 into the transmit FIFO.
N/A
D7
—
7
0
7
N/A
D6
—
6
0
6
THDLC1
Transmit HDLC FIFO Data
5Eh
THDLC2
Transmit HDLC FIFO Status
5Fh
N/A
D5
—
5
0
5
62 of 88
N/A
D4
—
0
4
4
N/A
D3
—
3
0
3
N/A
D2
—
2
0
2
N/A
D1
—
1
0
1
TMEND
D0
0
0
0
0