DS3141+ Maxim Integrated Products, DS3141+ Datasheet - Page 27

• Manufacturer Part Number: DS3141+
• Description: IC FRAMER DS3/E3 SNGL 144CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3141+

• Controller Type: DS3/E3 Framer
• Interface: LIU
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 80mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: TCLK Invert Enable (TCLKI)
Bit 1: TPOS/TNRZ Invert Enable (TPOSI)
Bit 2: TNEG Invert Enable (TNEGI)
Bit 3: TPOS/TNRZ Force-High Enable (TPOSH). The TPOS/TNRZ pin can be forced low by setting both the
TPOSH and TPOSI control bits.
Bit 4: TNEG Force-High Enable (TNEGH). The TNEG pin can be forced low by setting both the TNEGH and
TNEGI control bits.
Bit 5: RCLK Invert Enable (RCLKI)
Bit 6: RPOS/RNRZ Invert Enable (RPOSI)
Bit 7: RNEG/RLCV Invert Enable (RNEGI)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
This register is a global resource and is mapped into address 06h in every framer in the device. In both interrupt-based and polling-based
device servicing strategies, the host processor should read this register first to determine which framers require servicing.
Bit 0: Interrupt 1 (INT1). This bit is set when framer 1 is driving the INT pin.
Bit 1: Interrupt 2 (INT2). This bit is set when framer 2 is driving the INT pin.
Bit 2: Interrupt 3 (INT3). This bit is set when framer 3 is driving the INT pin.
Bit 3: Interrupt 4 (INT4). This bit is set when framer 4 is driving the INT pin.
0 = do not invert the TCLK signal (normal mode)
1 = invert the TCLK signal (inverted mode)
0 = do not invert the TPOS/TNRZ signal (normal mode)
1 = invert the TPOS/TNRZ signal (inverted mode)
0 = do not invert the TNEG signal (normal mode)
1 = invert the TNEG signal (inverted mode)
0 = allow normal transmit data to appear at the TPOS/TNRZ pin (normal mode)
1 = force the TPOS/TNRZ signal high (force high mode, can be inverted)
0 = allow normal transmit data to appear at the TNEG pin (normal mode)
1 = force the TNEG signal high (force high mode, can be inverted)
0 = do not invert the RCLK signal (normal mode)
1 = invert the RCLK signal (inverted mode)
0 = do not invert the RPOS/RNRZ signal (normal mode)
1 = invert the RPOS/RNRZ signal (inverted mode)
0 = do not invert the RNEG/RLCV signal (normal mode)
1 = invert the RNEG/RLCV signal (inverted mode)
RNEGI
N/A
7
0
—
7
RPOSI
6
0
N/A
—
6
ISR1
Interrupt Status Register 1
06h
MC5
Master Configuration Register 5
05h
RCLKI
5
0
N/A
—
5
TNEGH
27 of 88
N/A
4
0
—
4
TPOSH
INT4
—
3
0
3
TNEGI
INT3
—
2
0
2
TPOSI
INT2
—
1
0
1
TCLKI
INT1
—
0
0
0