DS3141+ Maxim Integrated Products, DS3141+ Datasheet - Page 49

• Manufacturer Part Number: DS3141+
• Description: IC FRAMER DS3/E3 SNGL 144CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3141+

• Controller Type: DS3/E3 Framer
• Interface: LIU
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 80mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: See
Bit 0: Synchronization Status Latched (SYNCL). This latched status bit is set to 1 when the SYNC status bit in
the
synchronization or losing synchronization, read the SYNC real-time status bit in the
cleared when the host processor writes a 1 to it and is not set again until SYNC changes state again. When
SYNCL is set, it can cause a hardware interrupt to occur if the SYNCIE bit in the
bit in the
interrupt-enable bits are cleared.
Bit 1: BERT Error-Counter Overflow Latched (BECOL). This latched status bit is set to 1 when the BECO status
bit in the
until BECO goes high again. When BECOL is set, it can cause a hardware interrupt to occur if the BECOIE bit in
the
bit is cleared or one or both of the interrupt-enable bits are cleared.
Bit 2: BERT Bit-Counter Overflow Latched (BBCOL). This latched status bit is set to 1 when the BBCO status bit
in the
BBCO goes high again. When BBCOL is set, it can cause a hardware interrupt to occur if the BBCOIE bit in the
BSRIE
cleared or one or both of the interrupt-enable bits are cleared.
Bit 3: Bit Error-Detected Latched (BEDL). This latched status bit is set to 1 when a bit error is detected. The
receive BERT must be in synchronization to detect bit errors. BEDL is cleared when the host processor writes a 1
to it. When BEDL is set it can cause a hardware interrupt to occur if the BEDIE bit in the
BERTIE bit in the
of the interrupt-enable bits are cleared.
Bit 4: Receive All-Zeros Latched (RA0L). This latched status bit is set to 1 when the RA0 bit in the
is set. RA0L is cleared when the host processor writes a 1 to it. RA0L cannot cause an interrupt.
Bit 5: Receive All-Ones Latched (RA1L). This latched status bit is set to 1 when the RA1 bit in the
set. RA1L is cleared when the host processor writes a 1 to it. RA1L cannot cause an interrupt.
BSRIE
BSR
BSR
register and the BERTIE bit in the
Figure 7-6
BSR
register changes state (low to high or high to low). To determine if this bit was set because of finding
MSRIE
register and the BERTIE bit in the
register goes high. BBCOL is cleared when the host processor writes a 1 to it and is not set again until
register goes high. BECOL is cleared when the host processor writes a one to it and is not set again
N/A
—
7
for details on the interrupt logic for the status bits in the BSRL register.
register are both set to 1. The interrupt is cleared when this bit is cleared or one or both of the
MSRIE
register are both set to 1. The interrupt is cleared when this bit is cleared or one or both
N/A
—
6
BSRL
BERT Status Register Latched
39h
RA1L
MSRIE
—
5
MSRIE
register are both set to 1. The interrupt is cleared when this bit is
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register are both set to a 1. The interrupt is cleared when this
RA0L
—
4
BEDL
—
3
BBCOL
—
2
BSRIE
BSR
register and the BERTIE
BSRIE
BECOL
—
1
register. SYNCL is
register and the
BSR
BSR
SYNCL
register is
—
register
0