DS3141+ Maxim Integrated Products, DS3141+ Datasheet - Page 37

• Manufacturer Part Number: DS3141+
• Description: IC FRAMER DS3/E3 SNGL 144CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3141+

• Controller Type: DS3/E3 Framer
• Interface: LIU
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 80mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: See
Bit 0: Loss-of-Signal Occurrence Latched (LOSL). This latched status bit is set to 1 when the LOS status bit in
the
to it. When LOSL is set, it can cause a hardware interrupt to occur if the LOSIE bit in the
the T3E3IE bit in the
both of the interrupt-enable bits are cleared. See the note in the LOS status bit description for further information.
Bit 1: Out-of-Frame Occurrence Latched (OOFL). This latched status bit is set to 1 when the OOF status bit in
the
1 to it. When OOFL is set, it can cause a hardware interrupt to occur if the OOFIE bit in the
the T3E3IE bit in the
both of the interrupt-enable bits are cleared.
Bit 2: Alarm Indication Signal Detected Latched (AISL). This latched status bit is set to 1 when the AIS status
bit in the
writes a 1 to it. When AISL is set, it can cause a hardware interrupt to occur if the AISIE bit in the
register and the T3E3IE bit in the
or one or both of the interrupt-enable bits are cleared.
Bit 3: Remote Alarm Indication Detected Latched (RAIL). This latched status bit is set to 1 when the RAI status
bit in the
writes a 1 to it. When RAIL is set, it can cause a hardware interrupt to occur if the RAIIE bit in the
register and the T3E3IE bit in the
or one or both of the interrupt-enable bits are cleared.
Bit 4: DS3 Idle-Signal-Detected Latched (T3IDLEL). This latched status bit is set to 1 when the T3IDLE status bit
in the
writes a 1 to it. When T3IDLEL is set, it can cause a hardware interrupt to occur if the T3IDLEIE bit in the
T3E3SRIE
is cleared or one or both of the interrupt-enable bits are cleared.
Bit 5: Severely Errored Frame Detected Latched (SEFL). This latched status bit is set to 1 when the SEF status
bit in the
writes a 1 to it. When SEFL is set, it can cause a hardware interrupt to occur if the SEFIE bit in the
register and the T3E3IE bit in the
or one or both of the interrupt-enable bits are cleared.
Bit 7: Change-of-Frame Alignment Latched (COFAL). This latched status bit is set to 1 when the DS3/E3 framer
has experienced a change of frame alignment (COFA). A COFA occurs when the framer achieves synchronization
in a different alignment than it had previously. If the framer has never acquired synchronization before, then this
status bit is meaningless. COFAL is cleared when the host processor writes a 1 to it and is not set again until the
framer has lost synchronization and reacquired synchronization in a different alignment. When COFAL is set, it can
cause a hardware interrupt to occur if the COFAIE bit in the
register are both set to 1. The interrupt is cleared when this bit is cleared or one or both of the interrupt-enable bits
are cleared.
T3E3SR
T3E3SR
T3E3SR
Figure 7-5
T3E3SR
T3E3SR
T3E3SR
register and the T3E3IE bit in the
register changes state (low to high or high to low). LOSL is cleared when the host processor writes a 1
register changes state (low to high or high to low). OOFL is cleared when the host processor writes a
COFAL
register changes state (low to high or high to low). T3IDLEL is cleared when the host processor
—
7
for details on the interrupt logic for the status bits in the T3E3SRL register.
register changes state (low to high or high to low). SEFL is cleared when the host processor
register changes state (low to high or high to low). AISL is cleared when the host processor
register changes state (low to high or high to low). RAIL is cleared when the host processor
MSRIE
MSRIE
N/A
—
register are both set to 1. The interrupt is cleared when this bit is cleared or one or
register are both set to 1. The interrupt is cleared when this bit is cleared or one or
6
T3E3SRL
DS3/E3 Status Register Latched
19h
MSRIE
MSRIE
MSRIE
SEFL
register are both set to 1. The interrupt is cleared when this bit is cleared
register are both set to 1. The interrupt is cleared when this bit is cleared
register are both set to 1. The interrupt is cleared when this bit is cleared
—
5
MSRIE
T3IDLEL
register are both set to 1. The interrupt is cleared when this bit
37 of 88
—
4
T3E3SRIE
RAIL
—
3
register and the T3E3IE bit in the
AISL
—
2
T3E3SRIE
T3E3SRIE
OOFL
—
1
register and
register and
T3E3SRIE
T3E3SRIE
T3E3SRIE
LOSL
—
0
MSRIE