IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 84

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
3.13.2.2
mit Side System Common Clock A (TSCCKA) and Transmit Side Sys-
tem Common Clock B (TSCCKB) provided by the system side are used
as one of the reference clocks for the transmit jitter attenuator DPLL for
all eight framers (refer to Chapter 3.20 Transmit Clock for details).
TSSIGn is used as TSFSn to output a framing pulse to indicate every F-
bit.
1.544Mb/s.
Functional Description
In the Transmit Clock Master mode (refer to Figure 43), the Trans-
In the Transmit Clock Master mode, the multi-functional pin TSFSn/
In the Transmit Clock Master mode, the bit rate on the TSDn pin is
TSFSn
TSFSn
TSFSn
TSFSn
TSDn
TSDn
LTCKn
TSDn
TSDn
Transmit Clock Master Mode
1
Figure 60. T1/J1 Transmit Clock Master Mode - Functional Timing Example
1
1
LTCKn is 1.544M
2
1
2
2
When the TSFSRISE (b5, T1/J1-004H) is logic 1 and the TSDFALL (b1, T1/J1-004) is logic 1:
When the TSFSRISE (b5, T1/J1-004H) is logic 0 and the TSDFALL (b1, T1/J1-004) is logic 0:
When the TSFSRISE (b5, T1/J1-004H) is logic 0 and the TSDFALL (b1, T1/J1-004) is logic 1:
When the TSFSRISE (b5, T1/J1-004H) is logic 1 and the TSDFALL (b1, T1/J1-004) is logic 0:
3
2
3
3
4
3
CH24
4
4
CH24
CH24
5
4
CH24
5
5
6
5
6
6
7
6
7
7
8
7
8
8
F
8
F
F
1
F
1
1
74
2
1
2
2
cessed clock signal on the LTCKn pin to sample/update the data on the
system interface. The active edge of LTCKn to sample the data on the
TSDn pin is determined by the TSDFALL (b1, T1/J1-004H). The active
edge of LTCKn to update the pulse on the TSFSn pin is determined by
the TSFSRISE (b5, T1/J1-004H).
channel is the first bit to be transmitted.
3
2
3
3
CH1
In the Transmit Clock Master mode, each framer uses its own pro-
Figure 60 shows the functional timing examples. Bit 1 of each
4
3
CH1
CH1
4
4
CH1
5
4
5
5
6
5
6
6
7
6
7
7
8
7
8
8
1
8
1
1
2
1
2
2
T1 / E1 / J1 OCTAL FRAMER
CH2
3
2
CH2
CH2
3
3
CH2
4
3
4
4
5
4
5
5
5
March 5, 2009