IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 114

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
transmit-receive integrity and system backplane integrity.
- Example For Testing E1 Line Transmit-Receive Integrity
off line, the following procedure should be done:
insertion/extraction of PRGD test data;
slots;
Table 48 should be set.
shows the process to initialize the TPLC. Table 48 shows the process to
initialize the RPLC.
Table 46: Setting of PRGD
Operation
Table 47: Initialization of TPLC
Register Value
0DCH
00CH
070H
072H
073H
078H
07BH
087H
0E0H
The PRBS generator/detector block can be used to test E1 line
To monitor the errors in Framer 2 without taking the entire E1 span
- Use the PRGD block to test Framer 2;
- Configure the PRGD register;
- Chose a desired set of time slots (for example TS2, TS4, TS5) for
- Set the far end of the line to loop back at least the selected time
- Monitor the E1 line transmit-receive integrity.
To realize the above function, the configuration in Table 46 to
Table 46 is the configuration for PRGD and loopback. Table 47
Register
20H Select Framer 2 to be tested by the PRGD block. The
82H Set Pattern Detector registers as error counter
18H Set the pattern length.
02H Set the feedback tap position.
FFH Set the Pattern Insertion registers.
FFH Load the data in the Pattern Insertion registers to generate
04H Set diagnostic digital loopback mode.
01H Enable the TPLC indirect registers to be accessible.
01H Enable the RPLC indirect registers to be accessible.
0E3H
0E2H
0E3H
0E2H
0E3H
0E2H
0E3H
0E2H
0E3H
0E2H
0E3H
PRGD pattern is inserted in the TPLC and detected in the
RPLC.
Enable automatic resynchronization.
the pattern.
Description
Value
00H
20H
00H
21H
00H
22H
00H
23H
00H
24H
00H
register.
104
Table 47: Initialization of TPLC (Continued)
Register
0E2H
0E3H
0E2H
0E3H
0E2H
0E3H
0E2H
0E3H
0E2H
0E3H
0E2H
0E3H
0E2H
0E3H
0E2H
0E3H
0E2H
0E3H
0E2H
0E3H
0E2H
0E3H
0E2H
0E3H
0E2H
0E3H
0E2H
0E3H
0E2H
0E3H
0E2H
0E3H
0E2H
0E3H
0E2H
0E3H
0E2H
0E3H
0E2H
0E3H
0E2H
0E3H
0E2H
0E3H
0E2H
0E3H
0E2H
T1 / E1 / J1 OCTAL FRAMER
Value
2AH
2BH
2CH
2DH
2EH
3AH
3BH
3CH
25H
00H
26H
00H
27H
00H
28H
00H
29H
00H
00H
00H
00H
00H
00H
2FH
00H
30H
00H
31H
00H
32H
00H
33H
00H
34H
00H
35H
00H
36H
00H
37H
00H
38H
00H
39H
00H
00H
00H
March 5, 2009