IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 79

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
3.13.2
multiplexed Mode or Multiplexed Mode. In the Non-multiplexed Mode,
the TSDn pin is used to input the data to each framer at a bit rate of
1.544 Mb/s or 2.048 Mb/s (T1/J1 mode E1 rate). While in the Multi-
plexed Mode, the data input to the eight framers is converted to 2.048
Mb/s format and byte-interleaved from two high speed data streams and
inputs on the MTSD1 and MTSD2 pins at a bit rate of 8.192 Mb/s.
on the TSDn pin is provided by the system side and shared by all eight
framers, the Transmit System Interface should be set in Transmit Clock
Slave mode. If the timing signal for clocking data on each TSDn pin is
provided from each line side (processed timing signal), the Transmit
System Interface should be set in Transmit Clock Master mode.
provided by the system side for the eight framers, the Transmit System
Interface should be set in Transmit Clock Slave mode. If there is not a
Table 33: T1/J1 Mode Transmit System Interface in Different Operation Modes
Functional Description
Table 34: Operation Mode Selection in T1/J1 Transmit Path
Note:
* When the RATE[1:0] are '00', the system clock rate is 1.544MHz.
Non-Multiplexed
When the RATE[1:0] are '01', the system clock rate is 2.048MHz, i.e., T1/J1 mode E1 rate.
In T1/J1 mode, the Transmit System Interface can be set in Non-
In the Non-multiplexed Mode, if the timing signal for clocking data
In the Non-multiplexed Mode, if there is a common framing pulse
Mode
RATE[1:0] (b3~2, T1/J1-005H)
11 (in any of the eight framers)
T1/J1 MODE
Clock Slave Mode
00 / 01 *
Multiplexed Mode
Operation Mode
00
Clock Master Mode
External Signaling
TSFS Enable
EMODE[1:0] (b7~6, T1/J1-005H)
Data Pin
MTSD
TSDn
TSDn
TSDn
10
11
01
11
69
MTSCCKB
common framing pulse, the Transmit System Interface should be set in
Transmit Clock Master mode.
TSSIGn is used to output the framing indication pulse, the Transmit Sys-
tem Interface is in Transmit Clock Slave TSFS Enable mode. If the
TSFSn/TSSIGn pin is used to input the signaling bits to be inserted, the
Transmit System Interface is in Transmit Clock Slave External Signaling
mode.
2.048 MHz in T1/J1 mode, can only be supported in the Transmit Clock
Slave mode.
TSSIGn is used as TSFSn to input the framing indication pulse.
operation modes. To set the transmit system interface of each framer
into various operation modes, the registers must be configured as
Table 34.
Clock Pin
TSCCKB
TSCCKB
LTCKn
In the Transmit Clock Slave mode, if the multi-function pin TSFSn/
The T1/J1 mode E1 rate, which means the system clock rate is
In the Transmit Clock Master mode, the multi-function pin TSFSn/
Table 33 summarizes the transmit system interface in different
TSCFS & TSFSn
Framing Pin
MTSCFS
TSCFS
TSFSn
Transmit Clock Slave External Signaling
Transmit Clock Slave TSFS Enable
Transmit Clock Master
Transmit Multiplexed
Operation Mode
Signaling Pin
MTSSIG
TSSIGn
T1 / E1 / J1 OCTAL FRAMER
No
No
Reference Clock Pin
TSCCKA & TSCCKB
March 5, 2009
TSCCKA
TSCCKA
TSCCKA